hpm_enet_drv.h

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/*
 * Copyright (c) 2021-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_ENET_DRV_H
#define HPM_ENET_DRV_H
 
/*---------------------------------------------------------------------
 * Includes
 *---------------------------------------------------------------------
 */
#include "hpm_common.h"
#include "hpm_enet_regs.h"
#include "hpm_soc_feature.h"
#include "hpm_enet_soc_drv.h"
 
/*---------------------------------------------------------------------
 *  Macro Constant Declarations
 *---------------------------------------------------------------------
 */
#define ENET_HEADER               (14U)    
#define ENET_VLAN_TAG             (4U)     
#define ENET_CRC                  (4U)     
#define ENET_MIN_PAYLOAD          (46U)    
#define ENET_MAX_PAYLOAD          (1500U)  
#define ENET_MAX_FRAME_SIZE       (1526U)  
#define ENET_JUMBO_FRAME_PAYLOAD  (9000U)  
#define ENET_MAC                  (6)      
#define ENET_ERROR                (0)      
#define ENET_SUCCESS              (1)      
#define ENET_ADJ_FREQ_BASE_ADDEND (0x80000000UL)  
#define ENET_ONE_SEC_IN_NANOSEC   (1000000000UL)  
#define ENET_PPS_CMD_MASK         (0x07UL) 
#define ENET_PPS_CMD_OFS_FAC      (3U)     
#ifndef ENET_RETRY_CNT
#define ENET_RETRY_CNT            (10000UL)   
#endif
 
#ifndef ENET_RETRY_DMA_INIT_CNT
#define ENET_RETRY_DMA_INIT_CNT   (10000000UL) 
#endif
 
#define ENET_MAX_BUFF_SIZE        ((ENET_MAX_FRAME_SIZE + (ENET_SOC_DMA_BUS_WIDTH_IN_BYTES - 1)) & ~(ENET_SOC_DMA_BUS_WIDTH_IN_BYTES - 1))
/*---------------------------------------------------------------------
 *  Typedef Enum Declarations
 *---------------------------------------------------------------------
 */
 
typedef enum {
    enet_normal_int_sum_en   = ENET_DMA_INTR_EN_NIE_MASK,
    enet_aboarmal_int_sum_en = ENET_DMA_INTR_EN_AIE_MASK,
    enet_receive_int_en      = ENET_DMA_INTR_EN_RIE_MASK,
    enet_transmit_int_en     = ENET_DMA_INTR_EN_TIE_MASK
} enet_interrupt_enable_t;
 
typedef enum {
    enet_lpi_int_mask    = ENET_INTR_MASK_LPIIM_MASK,
    enet_rgsmii_int_mask = ENET_INTR_MASK_RGSMIIIM_MASK
} enet_interrupt_mask_t;
 
 
typedef enum {
    enet_pbl_1  = 1,
    enet_pbl_2  = 2,
    enet_pbl_4  = 4,
    enet_pbl_8  = 8,
    enet_pbl_16 = 16,
    enet_pbl_32 = 32
} enet_pbl_t;
 
typedef enum {
    enet_cic_disable            = 0,
    enet_cic_ip                 = 1,
    enet_cic_ip_no_pseudoheader = 2,
    enet_cic_ip_pseudoheader    = 3
} enet_cic_insertion_control_t;
 
typedef enum {
    enet_vlic_disable          = 0,
    enet_vlic_remove_vlan_tag  = 1,
    enet_vlic_insert_vlan_tag  = 2,
    enet_vlic_replace_vlan_tag = 3
} enet_vlan_insertion_control_t;
 
typedef enum {
    enet_saic_disable      = 0,
    enet_saic_insert_mac0  = 1,
    enet_saic_replace_mac0 = 2,
    enet_saic_insert_mac1  = 5,
    enet_saic_replace_mac1 = 6
} enet_saic_insertion_replacement_control_t;
 
typedef enum {
    enet_sarc_disable      = 0,
    enet_sarc_insert_mac0  = 2,
    enet_sarc_replace_mac0 = 3,
    enet_sarc_insert_mac1  = 6,
    enet_sarc_replace_mac1 = 7
} enet_sarc_insertion_replacement_control_t;
 
typedef enum {
    enet_phy_op_read = 0,
    enet_phy_op_write
} enet_phy_op_t;
 
 
typedef enum {
    enet_gmii_idle = 0,
    enet_gmii_busy
} enet_gmii_status_t;
 
typedef enum {
    enet_csr_60m_to_100m_mdc_csr_div_42 = 0,    
    enet_csr_100m_to_150m_mdc_csr_div_62,       
    enet_csr_20m_to_35m_mdc_csr_div_16,         
    enet_csr_35m_to_60m_mdc_csr_div_26,         
    enet_csr_150m_to_250m_mdc_csr_div_102,      
    enet_csr_250m_to_300m_mdc_csr_div_124,      
    enet_csr_60m_to_100m_mdc_csr_div_4 = 8,     
    enet_csr_60m_to_100m_mdc_csr_div_6,         
    enet_csr_60m_to_100m_mdc_csr_div_8,         
    enet_csr_60m_to_100m_mdc_csr_div_10,        
    enet_csr_60m_to_100m_mdc_csr_div_12,        
    enet_csr_60m_to_100m_mdc_csr_div_14,        
    enet_csr_60m_to_100m_mdc_csr_div_16,        
    enet_csr_60m_to_100m_mdc_csr_div_18         
} enet_csr_clk_range_t;
 
typedef enum {
    enet_inf_mii  = 0,
    enet_inf_rmii = 4,
    enet_inf_rgmii = 1
} enet_inf_type_t;
 
typedef enum {
    enet_line_speed_1000mbps  = 0,
    enet_line_speed_10mbps    = 2,
    enet_line_speed_100mbps   = 3
} enet_line_speed_t;
 
typedef enum {
    enet_half_duplex = 0,
    enet_full_duplex
} enet_duplex_mode_t;
 
typedef enum {
    enet_ptp_time_coarse_update = 0,
    enet_ptp_time_fine_update
} enet_ptp_time_update_method_t;
 
typedef enum {
    enet_ptp_v1 = 0,
    enet_ptp_v2
} enet_ptp_version_t;
 
typedef enum {
    enet_ptp_frame_ipv4 = 0,
    enet_ptp_frame_ipv6,
    enet_ptp_frame_ethernet
} enet_ptp_frame_type_t;
 
typedef enum {
    enet_ts_ss_ptp_msg_0 = 0, /* SYNC, Follow_Up, Delay_Req, Delay_Resp */
    enet_ts_ss_ptp_msg_1 = 1, /* SYNC */
    enet_ts_ss_ptp_msg_2 = 3, /* Delay_Req */
    enet_ts_ss_ptp_msg_3 = 4, /* SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up */
    enet_ts_ss_ptp_msg_4 = 5, /* SYNC, Pdelay_Req, Pdelay_Resp */
    enet_ts_ss_ptp_msg_5 = 7, /* Delay_Req, Pdelay_Req, Pdelay_Resp */
    enet_ts_ss_ptp_msg_6 = 8, /* SYNC, Delay_Req */
    enet_ts_ss_ptp_msg_7 = 12 /* Pdelay_Req, Pdelay_Resp */
} enet_ts_ss_ptp_msg_t;
 
typedef enum {
    enet_ts_bin_rollover_control = 0,  /* timestamp rolls over after 0x7fffffff */
    enet_ts_dig_rollover_control       /* timestamp rolls over after 0x3b9ac9ff */
} enet_ts_rollover_control_t;
 
typedef enum {
    enet_pps_0 = -1,
    enet_pps_1 = 0,
    enet_pps_2 = 1,
    enet_pps_3 = 2
} enet_pps_idx_t;
 
typedef enum {
    enet_ptp_auxi_snapshot_trigger_0 = ENET_TS_CTRL_ATSEN0_MASK,
    enet_ptp_auxi_snapshot_trigger_1 = ENET_TS_CTRL_ATSEN1_MASK,
    enet_ptp_auxi_snapshot_trigger_2 = ENET_TS_CTRL_ATSEN2_MASK,
    enet_ptp_auxi_snapshot_trigger_3 = ENET_TS_CTRL_ATSEN3_MASK
} enet_ptp_auxi_snapshot_trigger_idx_t;
 
typedef enum {
    enet_pps_ctrl_pps = 0,
    enet_pps_ctrl_bin_2hz_digital_1hz,
    enet_pps_ctrl_bin_4hz_digital_2hz,
    enet_pps_ctrl_bin_8hz_digital_4hz,
    enet_pps_ctrl_bin_16hz_digital_8hz,
    enet_pps_ctrl_bin_32hz_digital_16hz,
    enet_pps_ctrl_bin_64hz_digital_32hz,
    enet_pps_ctrl_bin_128hz_digital_64hz,
    enet_pps_ctrl_bin_256hz_digital_128hz,
    enet_pps_ctrl_bin_512hz_digital_256hz,
    enet_pps_ctrl_bin_1024hz_digital_512hz,
    enet_pps_ctrl_bin_2048hz_digital_1024hz,
    enet_pps_ctrl_bin_4096hz_digital_2048hz,
    enet_pps_ctrl_bin_8192hz_digital_4096hz,
    enet_pps_ctrl_bin_16384hz_digital_8192hz,
    enet_pps_ctrl_bin_32768hz_digital_16384hz
} enet_pps_ctrl_t;
 
typedef enum {
    enet_pps_cmd_no_command = 0,
    enet_pps_cmd_start_single_pulse,
    enet_pps_cmd_start_pulse_train,
    enet_pps_cmd_cancel_start,
    enet_pps_cmd_stop_pulse_train_at_time,
    enet_pps_cmd_stop_pulse_train_immediately,
    enet_pps_cmd_cancel_stop_pulse_train
} enet_pps_cmd_t;
 
/*---------------------------------------------------------------------
 *  Typedef Struct Declarations
 *---------------------------------------------------------------------
 */
typedef struct {
    uint32_t buffer;
    uint32_t count;
    uint16_t size;
} enet_buff_config_t;
 
typedef struct {
    uint32_t mac_addr_high[ENET_SOC_ADDR_MAX_COUNT];
    uint32_t mac_addr_low[ENET_SOC_ADDR_MAX_COUNT];
    uint8_t  valid_max_count;
    uint8_t  dma_pbl;
    uint8_t  sarc;
} enet_mac_config_t;
 
typedef struct {
    union {
        uint32_t tdes0;
        struct {
            uint32_t db:   1; 
            uint32_t uf:   1; 
            uint32_t ed:   1; 
            uint32_t cc:   4; 
            uint32_t vf:   1; 
            uint32_t ec:   1; 
            uint32_t lc:   1; 
            uint32_t nc:   1; 
            uint32_t loc:  1; 
            uint32_t ipe:  1; 
            uint32_t ff:   1; 
            uint32_t jt:   1; 
            uint32_t es:   1; 
            uint32_t ihe:  1; 
            uint32_t ttss: 1; 
            uint32_t vlic: 2; 
            uint32_t tch:  1; 
            uint32_t ter:  1; 
            uint32_t cic:  2; 
            uint32_t crcr: 1; 
            uint32_t ttse: 1; 
            uint32_t dp:   1; 
            uint32_t dc:   1; 
            uint32_t fs:   1; 
            uint32_t ls:   1; 
            uint32_t ic:   1; 
            uint32_t own:  1; 
        } tdes0_bm;
    };
 
    union {
        uint32_t tdes1;
        struct {
            uint32_t tbs1    : 13; 
            uint32_t reserved:  3; 
            uint32_t tbs2    : 13; 
            uint32_t saic    :  3; 
        } tdes1_bm;
    };
 
    union {
        uint32_t tdes2;
        struct {
             uint32_t buffer1;  
        } tdes2_bm;
    };
 
    union {
        uint32_t tdes3;
        union {
            uint32_t buffer2;   
            uint32_t next_desc; 
        } tdes3_bm;
    };
 
#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN
    struct {
        uint32_t reserved;
    } tdes4_bm;
 
    struct {
        uint32_t reserved;
    } tdes5_bm;
 
    struct {
        uint32_t ttsl;  
    } tdes6_bm;
 
    struct {
        uint32_t ttsh;  
    } tdes7_bm;
#endif
} enet_tx_desc_t;
 
typedef struct {
    union {
        uint32_t rdes0;
 
        struct {
                uint32_t ex_sta_rx_addr      : 1;  
                uint32_t ce                  : 1;  
                uint32_t dbe                 : 1;  
                uint32_t re                  : 1;  
                uint32_t rwt                 : 1;  
                uint32_t ft                  : 1;  
                uint32_t lc                  : 1;  
                uint32_t ts_ip_gf            : 1;  
                uint32_t ls                  : 1;  
                uint32_t fs                  : 1;  
                uint32_t vlan                : 1;  
                uint32_t oe                  : 1;  
                uint32_t le                  : 1;  
                uint32_t saf                 : 1;  
                uint32_t dse                 : 1;  
                uint32_t es                  : 1;  
                uint32_t fl                  : 14; 
                uint32_t afm                 : 1;  
                uint32_t own                 : 1;  
        } rdes0_bm;
    };
 
    union {
        uint32_t rdes1;
        struct {
            uint32_t rbs1     : 13; 
            uint32_t reserved0: 1;  
            uint32_t rch      : 1;  
            uint32_t rer      : 1;  
            uint32_t rbs2     : 13; 
            uint32_t reserved1: 2;  
            uint32_t dic      : 1;  
        } rdes1_bm;
    };
 
    union {
        uint32_t rdes2;
        struct {
            uint32_t buffer1;       
        } rdes2_bm;
    };
 
    union {
        uint32_t rdes3;
        union {
            uint32_t buffer2;   
            uint32_t next_desc; 
        } rdes3_bm;
    };
 
#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN
    union {
        uint32_t rdes4;
        struct {
            uint32_t ip_payload_type     : 3; 
            uint32_t ip_header_err       : 1; 
            uint32_t ip_payload_err      : 1; 
            uint32_t ip_chksum_bypassed  : 1; 
            uint32_t ipv4_pkt_received   : 1; 
            uint32_t ipv6_pkt_received   : 1; 
            uint32_t msg_type            : 4; 
            uint32_t ptp_frame_type      : 1; 
            uint32_t ptp_version         : 1; 
            uint32_t ts_dp               : 1; 
            uint32_t reserved0           : 1; 
            uint32_t av_pkt_recv         : 1; 
            uint32_t av_tagged_pkt_recv  : 1; 
            uint32_t vlan_tag_pri_value  : 3; 
            uint32_t reserved1           : 3; 
            uint32_t l3_fm               : 1; 
            uint32_t l4_fm               : 1; 
            uint32_t l3_l4_fnl           : 2; 
            uint32_t reserved2           : 4; 
        } rdes4_bm;
    };
 
    struct {
        uint32_t reserved;
    } rdes5_bm;
 
    struct {
        uint32_t rtsl;  
    } rdes6_bm;
 
    struct {
        uint32_t rtsh;  
    } rdes7_bm;
#endif
} enet_rx_desc_t;
 
typedef struct{
    uint32_t length;
    uint32_t buffer;
    enet_rx_desc_t *rx_desc;
} enet_frame_t;
 
typedef struct  {
    enet_rx_desc_t *fs_rx_desc;
    enet_rx_desc_t *ls_rx_desc;
    uint32_t  seg_count;
} enet_rx_frame_info_t;
 
typedef struct {
    bool enable_ioc;        /* interrupt on completion */
    bool disable_crc;       /* disable CRC */
    bool disable_pad;       /* disable Pad */
    bool enable_ttse;       /* enable transmit timestamp */
    bool enable_crcr;       /* CRC replacement control */
    uint8_t cic;            /* checksum insertion control */
    uint8_t vlic;           /* VLAN insertion control */
    uint8_t saic;           /* SA insertion control */
} enet_tx_control_config_t;
 
typedef struct {
    enet_tx_desc_t *tx_desc_list_head;
    enet_rx_desc_t *rx_desc_list_head;
    enet_tx_desc_t *tx_desc_list_cur;
    enet_rx_desc_t *rx_desc_list_cur;
    enet_buff_config_t tx_buff_cfg;
    enet_buff_config_t rx_buff_cfg;
    enet_rx_frame_info_t rx_frame_info;
    enet_tx_control_config_t tx_control_config;
} enet_desc_t;
 
typedef struct {
    uint32_t sec;
    uint32_t nsec;
} enet_ptp_ts_system_t;
 
typedef struct {
    uint32_t sec;
    uint32_t nsec;
    uint8_t sign;
} enet_ptp_ts_update_t;
 
typedef struct {
    uint32_t sec;
    uint32_t nsec;
} enet_ptp_ts_target_t;
 
typedef struct {
    uint8_t ssinc;
    uint8_t timestamp_rollover_mode;
    uint8_t update_method;
    uint32_t addend;
} enet_ptp_config_t;
 
typedef struct {
    uint32_t pps_interval;
    uint32_t pps_width;
    uint32_t target_sec;
    uint32_t target_nsec;
} enet_pps_cmd_config_t;
 
typedef struct {
    uint32_t sec;
    uint32_t nsec;
} enet_ptp_ts_auxi_snapshot_t;
 
typedef struct {
    bool    auxi_snapshot_miss;
    uint8_t auxi_snapshot_count;
    uint8_t auxi_snapshot_id;
} enet_ptp_auxi_snapshot_status_t;
 
typedef struct {
    uint32_t int_enable;       /* DMA_INTR_EN */
    uint32_t int_mask;         /* INTR MASK */
    uint32_t mmc_intr_rx;
    uint32_t mmc_intr_mask_rx;
    uint32_t mmc_intr_tx;
    uint32_t mmc_intr_mask_tx;
} enet_int_config_t;
 
/*
 *  @brief Bit definition of TDES1
 */
#define ENET_DMATxDesc_TBS2  ((uint32_t)0x1FFF0000)  
#define ENET_DMATxDesc_TBS1  ((uint32_t)0x00001FFF)  
#if defined __cplusplus
extern "C" {
#endif /* __cplusplus */
/*---------------------------------------------------------------------
 * Exported Functions
 *---------------------------------------------------------------------
 */
void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config);
 
void enet_get_default_interrupt_config(ENET_Type *ptr, enet_int_config_t *config);
 
uint32_t enet_get_interrupt_status(ENET_Type *ptr);
 
void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask);
 
void enet_mask_mmc_tx_interrupt_event(ENET_Type *ptr, uint32_t mask);
 
uint32_t enet_get_mmc_rx_interrupt_status(ENET_Type *ptr);
uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr);
 
hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config);
 
void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed);
 
void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode);
 
uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr);
 
void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data);
 
void enet_rx_resume(ENET_Type *ptr);
 
uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info);
 
enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info);
 
enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count);
 
uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size);
 
uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size);
 
uint32_t enet_prepare_tx_desc_with_ts_record(ENET_Type *ptr,
                                             enet_tx_desc_t **parent_tx_desc_list_cur,
                                             enet_tx_control_config_t *config,
                                             uint16_t frame_length, uint16_t tx_buff_size,
                                             enet_ptp_ts_system_t *timestamp);
 
void enet_dma_tx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc);
 
void enet_dma_rx_desc_chain_init(ENET_Type *ptr,  enet_desc_t *desc);
 
void enet_dma_flush(ENET_Type *ptr);
 
void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config);
 
void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_update_t *timestamp);
 
void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_system_t *timestamp);
 
void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_ts_update_t *timeoffset);
 
void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj);
 
void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver);
 
hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_frame_type, bool enable);
 
void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg);
 
void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq);
 
hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx);
 
hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx);
 
 
void enet_mask_interrupt_event(ENET_Type *ptr, uint32_t mask);
 
void enet_unmask_interrupt_event(ENET_Type *ptr, uint32_t mask);
 
void enet_enable_ptp_auxiliary_snapshot(ENET_Type *ptr, enet_ptp_auxi_snapshot_trigger_idx_t idx);
 
void enet_disable_ptp_auxiliary_snapshot(ENET_Type *ptr, enet_ptp_auxi_snapshot_trigger_idx_t idx);
 
void enet_get_ptp_auxi_timestamp(ENET_Type *ptr, enet_ptp_ts_auxi_snapshot_t *timestamp);
 
void enet_get_ptp_auxi_snapshot_status(ENET_Type *ptr, enet_ptp_auxi_snapshot_status_t *status);
 
#if defined __cplusplus
}
#endif /* __cplusplus */
 
#endif /* HPM_ENET_DRV_H */