HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_gpu_regs.h File Reference

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Data Structures

struct  GPU_Type
 

Macros

#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK   (0x80000UL)
 
#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT   (19U)
 
#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SET(x)   (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK)
 
#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) >> GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_IDLE_VG_MASK   (0x40000UL)
 
#define GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT   (18U)
 
#define GPU_AQHICLOCKCONTROL_IDLE_VG_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE_VG_MASK) >> GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_IDLE2_D_MASK   (0x20000UL)
 
#define GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT   (17U)
 
#define GPU_AQHICLOCKCONTROL_IDLE2_D_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE2_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_IDLE3_D_MASK   (0x10000UL)
 
#define GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT   (16U)
 
#define GPU_AQHICLOCKCONTROL_IDLE3_D_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE3_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK   (0x2000U)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT   (13U)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SET(x)   (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK   (0x1000U)
 
#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT   (12U)
 
#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SET(x)   (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK)
 
#define GPU_AQHICLOCKCONTROL_SOFT_RESET_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) >> GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK   (0x800U)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT   (11U)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SET(x)   (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK   (0x400U)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT   (10U)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SET(x)   (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK)
 
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK   (0x200U)
 
#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT   (9U)
 
#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SET(x)   (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK)
 
#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK   (0x1FCU)
 
#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT   (2U)
 
#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SET(x)   (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK)
 
#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT)
 
#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK   (0x2U)
 
#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT   (1U)
 
#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SET(x)   (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK)
 
#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_GET(x)   (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) >> GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT)
 
#define GPU_AQHILDLE_AXI_LP_MASK   (0x80000000UL)
 
#define GPU_AQHILDLE_AXI_LP_SHIFT   (31U)
 
#define GPU_AQHILDLE_AXI_LP_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_AXI_LP_MASK) >> GPU_AQHILDLE_AXI_LP_SHIFT)
 
#define GPU_AQHILDLE_IDLE_BLT_MASK   (0x1000U)
 
#define GPU_AQHILDLE_IDLE_BLT_SHIFT   (12U)
 
#define GPU_AQHILDLE_IDLE_BLT_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_BLT_MASK) >> GPU_AQHILDLE_IDLE_BLT_SHIFT)
 
#define GPU_AQHILDLE_IDLE_TS_MASK   (0x800U)
 
#define GPU_AQHILDLE_IDLE_TS_SHIFT   (11U)
 
#define GPU_AQHILDLE_IDLE_TS_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TS_MASK) >> GPU_AQHILDLE_IDLE_TS_SHIFT)
 
#define GPU_AQHILDLE_IDLE_FP_MASK   (0x400U)
 
#define GPU_AQHILDLE_IDLE_FP_SHIFT   (10U)
 
#define GPU_AQHILDLE_IDLE_FP_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FP_MASK) >> GPU_AQHILDLE_IDLE_FP_SHIFT)
 
#define GPU_AQHILDLE_IDLE_IM_MASK   (0x200U)
 
#define GPU_AQHILDLE_IDLE_IM_SHIFT   (9U)
 
#define GPU_AQHILDLE_IDLE_IM_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_IM_MASK) >> GPU_AQHILDLE_IDLE_IM_SHIFT)
 
#define GPU_AQHILDLE_IDLE_VG_MASK   (0x100U)
 
#define GPU_AQHILDLE_IDLE_VG_SHIFT   (8U)
 
#define GPU_AQHILDLE_IDLE_VG_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_VG_MASK) >> GPU_AQHILDLE_IDLE_VG_SHIFT)
 
#define GPU_AQHILDLE_IDLE_TX_MASK   (0x80U)
 
#define GPU_AQHILDLE_IDLE_TX_SHIFT   (7U)
 
#define GPU_AQHILDLE_IDLE_TX_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TX_MASK) >> GPU_AQHILDLE_IDLE_TX_SHIFT)
 
#define GPU_AQHILDLE_IDLE_RA_MASK   (0x40U)
 
#define GPU_AQHILDLE_IDLE_RA_SHIFT   (6U)
 
#define GPU_AQHILDLE_IDLE_RA_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_RA_MASK) >> GPU_AQHILDLE_IDLE_RA_SHIFT)
 
#define GPU_AQHILDLE_IDLE_SE_MASK   (0x20U)
 
#define GPU_AQHILDLE_IDLE_SE_SHIFT   (5U)
 
#define GPU_AQHILDLE_IDLE_SE_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SE_MASK) >> GPU_AQHILDLE_IDLE_SE_SHIFT)
 
#define GPU_AQHILDLE_IDLE_PA_MASK   (0x10U)
 
#define GPU_AQHILDLE_IDLE_PA_SHIFT   (4U)
 
#define GPU_AQHILDLE_IDLE_PA_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PA_MASK) >> GPU_AQHILDLE_IDLE_PA_SHIFT)
 
#define GPU_AQHILDLE_IDLE_SH_MASK   (0x8U)
 
#define GPU_AQHILDLE_IDLE_SH_SHIFT   (3U)
 
#define GPU_AQHILDLE_IDLE_SH_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SH_MASK) >> GPU_AQHILDLE_IDLE_SH_SHIFT)
 
#define GPU_AQHILDLE_IDLE_PE_MASK   (0x4U)
 
#define GPU_AQHILDLE_IDLE_PE_SHIFT   (2U)
 
#define GPU_AQHILDLE_IDLE_PE_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PE_MASK) >> GPU_AQHILDLE_IDLE_PE_SHIFT)
 
#define GPU_AQHILDLE_IDLE_DE_MASK   (0x2U)
 
#define GPU_AQHILDLE_IDLE_DE_SHIFT   (1U)
 
#define GPU_AQHILDLE_IDLE_DE_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_DE_MASK) >> GPU_AQHILDLE_IDLE_DE_SHIFT)
 
#define GPU_AQHILDLE_IDLE_FE_MASK   (0x1U)
 
#define GPU_AQHILDLE_IDLE_FE_SHIFT   (0U)
 
#define GPU_AQHILDLE_IDLE_FE_GET(x)   (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FE_MASK) >> GPU_AQHILDLE_IDLE_FE_SHIFT)
 
#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK   (0xFFFFFFFFUL)
 
#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT   (0U)
 
#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_GET(x)   (((uint32_t)(x) & GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK) >> GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT)
 
#define GPU_AQINTRENBL_INTR_ENBL_VEC_MASK   (0xFFFFFFFFUL)
 
#define GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT   (0U)
 
#define GPU_AQINTRENBL_INTR_ENBL_VEC_SET(x)   (((uint32_t)(x) << GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK)
 
#define GPU_AQINTRENBL_INTR_ENBL_VEC_GET(x)   (((uint32_t)(x) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) >> GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT)
 
#define GPU_GCCHIPREV_REV_MASK   (0xFFFFFFFFUL)
 
#define GPU_GCCHIPREV_REV_SHIFT   (0U)
 
#define GPU_GCCHIPREV_REV_GET(x)   (((uint32_t)(x) & GPU_GCCHIPREV_REV_MASK) >> GPU_GCCHIPREV_REV_SHIFT)
 
#define GPU_GCCHIPDATE_DATE_MASK   (0xFFFFFFFFUL)
 
#define GPU_GCCHIPDATE_DATE_SHIFT   (0U)
 
#define GPU_GCCHIPDATE_DATE_GET(x)   (((uint32_t)(x) & GPU_GCCHIPDATE_DATE_MASK) >> GPU_GCCHIPDATE_DATE_SHIFT)
 
#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK   (0xFFU)
 
#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT   (0U)
 
#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_GET(x)   (((uint32_t)(x) & GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK) >> GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT)
 
#define GPU_GCPRODUCTID_TYPE_MASK   (0xF000000UL)
 
#define GPU_GCPRODUCTID_TYPE_SHIFT   (24U)
 
#define GPU_GCPRODUCTID_TYPE_GET(x)   (((uint32_t)(x) & GPU_GCPRODUCTID_TYPE_MASK) >> GPU_GCPRODUCTID_TYPE_SHIFT)
 
#define GPU_GCPRODUCTID_NUM_MASK   (0xFFFFF0UL)
 
#define GPU_GCPRODUCTID_NUM_SHIFT   (4U)
 
#define GPU_GCPRODUCTID_NUM_GET(x)   (((uint32_t)(x) & GPU_GCPRODUCTID_NUM_MASK) >> GPU_GCPRODUCTID_NUM_SHIFT)
 
#define GPU_GCPRODUCTID_GRADE_LEVEL_MASK   (0xFU)
 
#define GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT   (0U)
 
#define GPU_GCPRODUCTID_GRADE_LEVEL_GET(x)   (((uint32_t)(x) & GPU_GCPRODUCTID_GRADE_LEVEL_MASK) >> GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT)
 
#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK   (0xFFFF0000UL)
 
#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT   (16U)
 
#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK)
 
#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT)
 
#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK   (0xF0U)
 
#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT   (4U)
 
#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK)
 
#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT)
 
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK   (0x4U)
 
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT   (2U)
 
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK)
 
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT)
 
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK   (0x2U)
 
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT   (1U)
 
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK)
 
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT)
 
#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK   (0x1U)
 
#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT   (0U)
 
#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK)
 
#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK   (0x1000U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT   (12U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK   (0x800U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT   (11U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK   (0x200U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT   (9U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK   (0x100U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT   (8U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK   (0x4U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT   (2U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK   (0x1U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT   (0U)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SET(x)   (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK)
 
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK   (0x1000U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT   (12U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK   (0x800U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT   (11U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK   (0x200U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT   (9U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK   (0x100U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT   (8U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK   (0x4U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT   (2U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK   (0x1U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT   (0U)
 
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_GET(x)   (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT)
 
#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK   (0xFFFFF000UL)
 
#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT   (12U)
 
#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SET(x)   (((uint32_t)(x) << GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK)
 
#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_GET(x)   (((uint32_t)(x) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) >> GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT)
 
#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK   (0x3F000000UL)
 
#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT   (24U)
 
#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SET(x)   (((uint32_t)(x) << GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK)
 
#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_GET(x)   (((uint32_t)(x) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) >> GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT)
 
#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK   (0xFFU)
 
#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT   (0U)
 
#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SET(x)   (((uint32_t)(x) << GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK)
 
#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_GET(x)   (((uint32_t)(x) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) >> GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT)
 
#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK   (0x100000UL)
 
#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT   (20U)
 
#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SET(x)   (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK)
 
#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_GET(x)   (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) >> GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT)
 
#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK   (0xC0000UL)
 
#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT   (18U)
 
#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SET(x)   (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK)
 
#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_GET(x)   (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT)
 
#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK   (0x30000UL)
 
#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT   (16U)
 
#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SET(x)   (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK)
 
#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_GET(x)   (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT)
 
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK   (0xFF00U)
 
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT   (8U)
 
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SET(x)   (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK)
 
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_GET(x)   (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT)
 
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK   (0xFFU)
 
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT   (0U)
 
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SET(x)   (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK)
 
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_GET(x)   (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT)
 
#define GPU_GCREGFETCHADDRESS_ADDRESS_MASK   (0xFFFFFFFCUL)
 
#define GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT   (2U)
 
#define GPU_GCREGFETCHADDRESS_ADDRESS_SET(x)   (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK)
 
#define GPU_GCREGFETCHADDRESS_ADDRESS_GET(x)   (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT)
 
#define GPU_GCREGFETCHADDRESS_TYPE_MASK   (0x3U)
 
#define GPU_GCREGFETCHADDRESS_TYPE_SHIFT   (0U)
 
#define GPU_GCREGFETCHADDRESS_TYPE_SET(x)   (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_TYPE_SHIFT) & GPU_GCREGFETCHADDRESS_TYPE_MASK)
 
#define GPU_GCREGFETCHADDRESS_TYPE_GET(x)   (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_TYPE_MASK) >> GPU_GCREGFETCHADDRESS_TYPE_SHIFT)
 
#define GPU_GCREGFETCHCONTROL_COUNT_MASK   (0x1FFFFFUL)
 
#define GPU_GCREGFETCHCONTROL_COUNT_SHIFT   (0U)
 
#define GPU_GCREGFETCHCONTROL_COUNT_SET(x)   (((uint32_t)(x) << GPU_GCREGFETCHCONTROL_COUNT_SHIFT) & GPU_GCREGFETCHCONTROL_COUNT_MASK)
 
#define GPU_GCREGFETCHCONTROL_COUNT_GET(x)   (((uint32_t)(x) & GPU_GCREGFETCHCONTROL_COUNT_MASK) >> GPU_GCREGFETCHCONTROL_COUNT_SHIFT)
 
#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK   (0xFFFFFFFFUL)
 
#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT   (0U)
 
#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_GET(x)   (((uint32_t)(x) & GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT)
 

Macro Definition Documentation

◆ GPU_AQHICLOCKCONTROL_CLK2D_DIS_GET

#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) >> GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT)

◆ GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK

#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK   (0x2U)

◆ GPU_AQHICLOCKCONTROL_CLK2D_DIS_SET

#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SET (   x)    (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK)

◆ GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT

#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT   (1U)

◆ GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_GET

#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT)

◆ GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK

#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK   (0x800U)

◆ GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SET

#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SET (   x)    (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK)

◆ GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT

#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT   (11U)

◆ GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_GET

#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT)

◆ GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK

#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK   (0x400U)

◆ GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SET

#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SET (   x)    (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK)

◆ GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT

#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT   (10U)

◆ GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_GET

#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT)

◆ GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK

#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK   (0x2000U)

◆ GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SET

#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SET (   x)    (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK)

◆ GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT

#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT   (13U)

◆ GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_GET

#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT)

◆ GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK

#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK   (0x200U)

◆ GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SET

#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SET (   x)    (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK)

◆ GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT

#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT   (9U)

◆ GPU_AQHICLOCKCONTROL_FSCALE_VAL_GET

#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT)

◆ GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK

#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK   (0x1FCU)

◆ GPU_AQHICLOCKCONTROL_FSCALE_VAL_SET

#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SET (   x)    (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK)

◆ GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT

#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT   (2U)

◆ GPU_AQHICLOCKCONTROL_IDLE2_D_GET

#define GPU_AQHICLOCKCONTROL_IDLE2_D_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE2_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT)

◆ GPU_AQHICLOCKCONTROL_IDLE2_D_MASK

#define GPU_AQHICLOCKCONTROL_IDLE2_D_MASK   (0x20000UL)

◆ GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT

#define GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT   (17U)

◆ GPU_AQHICLOCKCONTROL_IDLE3_D_GET

#define GPU_AQHICLOCKCONTROL_IDLE3_D_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE3_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT)

◆ GPU_AQHICLOCKCONTROL_IDLE3_D_MASK

#define GPU_AQHICLOCKCONTROL_IDLE3_D_MASK   (0x10000UL)

◆ GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT

#define GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT   (16U)

◆ GPU_AQHICLOCKCONTROL_IDLE_VG_GET

#define GPU_AQHICLOCKCONTROL_IDLE_VG_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE_VG_MASK) >> GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT)

◆ GPU_AQHICLOCKCONTROL_IDLE_VG_MASK

#define GPU_AQHICLOCKCONTROL_IDLE_VG_MASK   (0x40000UL)

◆ GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT

#define GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT   (18U)

◆ GPU_AQHICLOCKCONTROL_ISOLATE_GPU_GET

#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) >> GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT)

◆ GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK

#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK   (0x80000UL)

◆ GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SET

#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SET (   x)    (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK)

◆ GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT

#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT   (19U)

◆ GPU_AQHICLOCKCONTROL_SOFT_RESET_GET

#define GPU_AQHICLOCKCONTROL_SOFT_RESET_GET (   x)    (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) >> GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT)

◆ GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK

#define GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK   (0x1000U)

◆ GPU_AQHICLOCKCONTROL_SOFT_RESET_SET

#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SET (   x)    (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK)

◆ GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT

#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT   (12U)

◆ GPU_AQHILDLE_AXI_LP_GET

#define GPU_AQHILDLE_AXI_LP_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_AXI_LP_MASK) >> GPU_AQHILDLE_AXI_LP_SHIFT)

◆ GPU_AQHILDLE_AXI_LP_MASK

#define GPU_AQHILDLE_AXI_LP_MASK   (0x80000000UL)

◆ GPU_AQHILDLE_AXI_LP_SHIFT

#define GPU_AQHILDLE_AXI_LP_SHIFT   (31U)

◆ GPU_AQHILDLE_IDLE_BLT_GET

#define GPU_AQHILDLE_IDLE_BLT_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_BLT_MASK) >> GPU_AQHILDLE_IDLE_BLT_SHIFT)

◆ GPU_AQHILDLE_IDLE_BLT_MASK

#define GPU_AQHILDLE_IDLE_BLT_MASK   (0x1000U)

◆ GPU_AQHILDLE_IDLE_BLT_SHIFT

#define GPU_AQHILDLE_IDLE_BLT_SHIFT   (12U)

◆ GPU_AQHILDLE_IDLE_DE_GET

#define GPU_AQHILDLE_IDLE_DE_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_DE_MASK) >> GPU_AQHILDLE_IDLE_DE_SHIFT)

◆ GPU_AQHILDLE_IDLE_DE_MASK

#define GPU_AQHILDLE_IDLE_DE_MASK   (0x2U)

◆ GPU_AQHILDLE_IDLE_DE_SHIFT

#define GPU_AQHILDLE_IDLE_DE_SHIFT   (1U)

◆ GPU_AQHILDLE_IDLE_FE_GET

#define GPU_AQHILDLE_IDLE_FE_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FE_MASK) >> GPU_AQHILDLE_IDLE_FE_SHIFT)

◆ GPU_AQHILDLE_IDLE_FE_MASK

#define GPU_AQHILDLE_IDLE_FE_MASK   (0x1U)

◆ GPU_AQHILDLE_IDLE_FE_SHIFT

#define GPU_AQHILDLE_IDLE_FE_SHIFT   (0U)

◆ GPU_AQHILDLE_IDLE_FP_GET

#define GPU_AQHILDLE_IDLE_FP_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FP_MASK) >> GPU_AQHILDLE_IDLE_FP_SHIFT)

◆ GPU_AQHILDLE_IDLE_FP_MASK

#define GPU_AQHILDLE_IDLE_FP_MASK   (0x400U)

◆ GPU_AQHILDLE_IDLE_FP_SHIFT

#define GPU_AQHILDLE_IDLE_FP_SHIFT   (10U)

◆ GPU_AQHILDLE_IDLE_IM_GET

#define GPU_AQHILDLE_IDLE_IM_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_IM_MASK) >> GPU_AQHILDLE_IDLE_IM_SHIFT)

◆ GPU_AQHILDLE_IDLE_IM_MASK

#define GPU_AQHILDLE_IDLE_IM_MASK   (0x200U)

◆ GPU_AQHILDLE_IDLE_IM_SHIFT

#define GPU_AQHILDLE_IDLE_IM_SHIFT   (9U)

◆ GPU_AQHILDLE_IDLE_PA_GET

#define GPU_AQHILDLE_IDLE_PA_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PA_MASK) >> GPU_AQHILDLE_IDLE_PA_SHIFT)

◆ GPU_AQHILDLE_IDLE_PA_MASK

#define GPU_AQHILDLE_IDLE_PA_MASK   (0x10U)

◆ GPU_AQHILDLE_IDLE_PA_SHIFT

#define GPU_AQHILDLE_IDLE_PA_SHIFT   (4U)

◆ GPU_AQHILDLE_IDLE_PE_GET

#define GPU_AQHILDLE_IDLE_PE_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PE_MASK) >> GPU_AQHILDLE_IDLE_PE_SHIFT)

◆ GPU_AQHILDLE_IDLE_PE_MASK

#define GPU_AQHILDLE_IDLE_PE_MASK   (0x4U)

◆ GPU_AQHILDLE_IDLE_PE_SHIFT

#define GPU_AQHILDLE_IDLE_PE_SHIFT   (2U)

◆ GPU_AQHILDLE_IDLE_RA_GET

#define GPU_AQHILDLE_IDLE_RA_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_RA_MASK) >> GPU_AQHILDLE_IDLE_RA_SHIFT)

◆ GPU_AQHILDLE_IDLE_RA_MASK

#define GPU_AQHILDLE_IDLE_RA_MASK   (0x40U)

◆ GPU_AQHILDLE_IDLE_RA_SHIFT

#define GPU_AQHILDLE_IDLE_RA_SHIFT   (6U)

◆ GPU_AQHILDLE_IDLE_SE_GET

#define GPU_AQHILDLE_IDLE_SE_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SE_MASK) >> GPU_AQHILDLE_IDLE_SE_SHIFT)

◆ GPU_AQHILDLE_IDLE_SE_MASK

#define GPU_AQHILDLE_IDLE_SE_MASK   (0x20U)

◆ GPU_AQHILDLE_IDLE_SE_SHIFT

#define GPU_AQHILDLE_IDLE_SE_SHIFT   (5U)

◆ GPU_AQHILDLE_IDLE_SH_GET

#define GPU_AQHILDLE_IDLE_SH_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SH_MASK) >> GPU_AQHILDLE_IDLE_SH_SHIFT)

◆ GPU_AQHILDLE_IDLE_SH_MASK

#define GPU_AQHILDLE_IDLE_SH_MASK   (0x8U)

◆ GPU_AQHILDLE_IDLE_SH_SHIFT

#define GPU_AQHILDLE_IDLE_SH_SHIFT   (3U)

◆ GPU_AQHILDLE_IDLE_TS_GET

#define GPU_AQHILDLE_IDLE_TS_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TS_MASK) >> GPU_AQHILDLE_IDLE_TS_SHIFT)

◆ GPU_AQHILDLE_IDLE_TS_MASK

#define GPU_AQHILDLE_IDLE_TS_MASK   (0x800U)

◆ GPU_AQHILDLE_IDLE_TS_SHIFT

#define GPU_AQHILDLE_IDLE_TS_SHIFT   (11U)

◆ GPU_AQHILDLE_IDLE_TX_GET

#define GPU_AQHILDLE_IDLE_TX_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TX_MASK) >> GPU_AQHILDLE_IDLE_TX_SHIFT)

◆ GPU_AQHILDLE_IDLE_TX_MASK

#define GPU_AQHILDLE_IDLE_TX_MASK   (0x80U)

◆ GPU_AQHILDLE_IDLE_TX_SHIFT

#define GPU_AQHILDLE_IDLE_TX_SHIFT   (7U)

◆ GPU_AQHILDLE_IDLE_VG_GET

#define GPU_AQHILDLE_IDLE_VG_GET (   x)    (((uint32_t)(x) & GPU_AQHILDLE_IDLE_VG_MASK) >> GPU_AQHILDLE_IDLE_VG_SHIFT)

◆ GPU_AQHILDLE_IDLE_VG_MASK

#define GPU_AQHILDLE_IDLE_VG_MASK   (0x100U)

◆ GPU_AQHILDLE_IDLE_VG_SHIFT

#define GPU_AQHILDLE_IDLE_VG_SHIFT   (8U)

◆ GPU_AQINTRACKNOWLEDGE_INTR_VEC_GET

#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_GET (   x)    (((uint32_t)(x) & GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK) >> GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT)

◆ GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK

#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK   (0xFFFFFFFFUL)

◆ GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT

#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT   (0U)

◆ GPU_AQINTRENBL_INTR_ENBL_VEC_GET

#define GPU_AQINTRENBL_INTR_ENBL_VEC_GET (   x)    (((uint32_t)(x) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) >> GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT)

◆ GPU_AQINTRENBL_INTR_ENBL_VEC_MASK

#define GPU_AQINTRENBL_INTR_ENBL_VEC_MASK   (0xFFFFFFFFUL)

◆ GPU_AQINTRENBL_INTR_ENBL_VEC_SET

#define GPU_AQINTRENBL_INTR_ENBL_VEC_SET (   x)    (((uint32_t)(x) << GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK)

◆ GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT

#define GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT   (0U)

◆ GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_GET

#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_GET (   x)    (((uint32_t)(x) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) >> GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT)

◆ GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK

#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK   (0xFFU)

◆ GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SET

#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SET (   x)    (((uint32_t)(x) << GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK)

◆ GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT

#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT   (0U)

◆ GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_GET

#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_GET (   x)    (((uint32_t)(x) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) >> GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT)

◆ GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK

#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK   (0x3F000000UL)

◆ GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SET

#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SET (   x)    (((uint32_t)(x) << GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK)

◆ GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT

#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT   (24U)

◆ GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_GET

#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_GET (   x)    (((uint32_t)(x) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) >> GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT)

◆ GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK

#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK   (0xFFFFF000UL)

◆ GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SET

#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SET (   x)    (((uint32_t)(x) << GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK)

◆ GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT

#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT   (12U)

◆ GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_GET

#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_GET (   x)    (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT)

◆ GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK

#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK   (0x30000UL)

◆ GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SET

#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SET (   x)    (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK)

◆ GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT

#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT   (16U)

◆ GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_GET

#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_GET (   x)    (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT)

◆ GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK

#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK   (0xC0000UL)

◆ GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SET

#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SET (   x)    (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK)

◆ GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT

#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT   (18U)

◆ GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_GET

#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_GET (   x)    (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT)

◆ GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK

#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK   (0xFFU)

◆ GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SET

#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SET (   x)    (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK)

◆ GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT

#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT   (0U)

◆ GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_GET

#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_GET (   x)    (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT)

◆ GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK

#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK   (0xFF00U)

◆ GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SET

#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SET (   x)    (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK)

◆ GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT

#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT   (8U)

◆ GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_GET

#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_GET (   x)    (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) >> GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT)

◆ GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK

#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK   (0x100000UL)

◆ GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SET

#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SET (   x)    (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK)

◆ GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT

#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT   (20U)

◆ GPU_GCCHIPDATE_DATE_GET

#define GPU_GCCHIPDATE_DATE_GET (   x)    (((uint32_t)(x) & GPU_GCCHIPDATE_DATE_MASK) >> GPU_GCCHIPDATE_DATE_SHIFT)

◆ GPU_GCCHIPDATE_DATE_MASK

#define GPU_GCCHIPDATE_DATE_MASK   (0xFFFFFFFFUL)

◆ GPU_GCCHIPDATE_DATE_SHIFT

#define GPU_GCCHIPDATE_DATE_SHIFT   (0U)

◆ GPU_GCCHIPREV_REV_GET

#define GPU_GCCHIPREV_REV_GET (   x)    (((uint32_t)(x) & GPU_GCCHIPREV_REV_MASK) >> GPU_GCCHIPREV_REV_SHIFT)

◆ GPU_GCCHIPREV_REV_MASK

#define GPU_GCCHIPREV_REV_MASK   (0xFFFFFFFFUL)

◆ GPU_GCCHIPREV_REV_SHIFT

#define GPU_GCCHIPREV_REV_SHIFT   (0U)

◆ GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_GET

#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT)

◆ GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK

#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK   (0x2U)

◆ GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SET

#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK)

◆ GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT

#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT   (1U)

◆ GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_GET

#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT)

◆ GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK

#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK   (0x4U)

◆ GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SET

#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK)

◆ GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT

#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT   (2U)

◆ GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_GET

#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT)

◆ GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK

#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK   (0x1U)

◆ GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SET

#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK)

◆ GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT

#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT   (0U)

◆ GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_GET

#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT)

◆ GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK

#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK   (0xFFFF0000UL)

◆ GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SET

#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK)

◆ GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT

#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT   (16U)

◆ GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_GET

#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT)

◆ GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK

#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK   (0xF0U)

◆ GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SET

#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK)

◆ GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT

#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT   (4U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_GET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK   (0x1U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT   (0U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_GET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK   (0x200U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT   (9U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_GET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK   (0x4U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT   (2U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_GET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK   (0x800U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT   (11U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_GET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK   (0x100U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT   (8U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_GET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK   (0x1000U)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SET

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SET (   x)    (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK)

◆ GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT

#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT   (12U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_GET

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK   (0x1U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT   (0U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_GET

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK   (0x1000U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT   (12U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_GET

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK   (0x200U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT   (9U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_GET

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK   (0x4U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT   (2U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_GET

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK   (0x800U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT   (11U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_GET

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_GET (   x)    (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK   (0x100U)

◆ GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT

#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT   (8U)

◆ GPU_GCPRODUCTID_GRADE_LEVEL_GET

#define GPU_GCPRODUCTID_GRADE_LEVEL_GET (   x)    (((uint32_t)(x) & GPU_GCPRODUCTID_GRADE_LEVEL_MASK) >> GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT)

◆ GPU_GCPRODUCTID_GRADE_LEVEL_MASK

#define GPU_GCPRODUCTID_GRADE_LEVEL_MASK   (0xFU)

◆ GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT

#define GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT   (0U)

◆ GPU_GCPRODUCTID_NUM_GET

#define GPU_GCPRODUCTID_NUM_GET (   x)    (((uint32_t)(x) & GPU_GCPRODUCTID_NUM_MASK) >> GPU_GCPRODUCTID_NUM_SHIFT)

◆ GPU_GCPRODUCTID_NUM_MASK

#define GPU_GCPRODUCTID_NUM_MASK   (0xFFFFF0UL)

◆ GPU_GCPRODUCTID_NUM_SHIFT

#define GPU_GCPRODUCTID_NUM_SHIFT   (4U)

◆ GPU_GCPRODUCTID_TYPE_GET

#define GPU_GCPRODUCTID_TYPE_GET (   x)    (((uint32_t)(x) & GPU_GCPRODUCTID_TYPE_MASK) >> GPU_GCPRODUCTID_TYPE_SHIFT)

◆ GPU_GCPRODUCTID_TYPE_MASK

#define GPU_GCPRODUCTID_TYPE_MASK   (0xF000000UL)

◆ GPU_GCPRODUCTID_TYPE_SHIFT

#define GPU_GCPRODUCTID_TYPE_SHIFT   (24U)

◆ GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_GET

#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_GET (   x)    (((uint32_t)(x) & GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT)

◆ GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK

#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK   (0xFFFFFFFFUL)

◆ GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT

#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT   (0U)

◆ GPU_GCREGFETCHADDRESS_ADDRESS_GET

#define GPU_GCREGFETCHADDRESS_ADDRESS_GET (   x)    (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT)

◆ GPU_GCREGFETCHADDRESS_ADDRESS_MASK

#define GPU_GCREGFETCHADDRESS_ADDRESS_MASK   (0xFFFFFFFCUL)

◆ GPU_GCREGFETCHADDRESS_ADDRESS_SET

#define GPU_GCREGFETCHADDRESS_ADDRESS_SET (   x)    (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK)

◆ GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT

#define GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT   (2U)

◆ GPU_GCREGFETCHADDRESS_TYPE_GET

#define GPU_GCREGFETCHADDRESS_TYPE_GET (   x)    (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_TYPE_MASK) >> GPU_GCREGFETCHADDRESS_TYPE_SHIFT)

◆ GPU_GCREGFETCHADDRESS_TYPE_MASK

#define GPU_GCREGFETCHADDRESS_TYPE_MASK   (0x3U)

◆ GPU_GCREGFETCHADDRESS_TYPE_SET

#define GPU_GCREGFETCHADDRESS_TYPE_SET (   x)    (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_TYPE_SHIFT) & GPU_GCREGFETCHADDRESS_TYPE_MASK)

◆ GPU_GCREGFETCHADDRESS_TYPE_SHIFT

#define GPU_GCREGFETCHADDRESS_TYPE_SHIFT   (0U)

◆ GPU_GCREGFETCHCONTROL_COUNT_GET

#define GPU_GCREGFETCHCONTROL_COUNT_GET (   x)    (((uint32_t)(x) & GPU_GCREGFETCHCONTROL_COUNT_MASK) >> GPU_GCREGFETCHCONTROL_COUNT_SHIFT)

◆ GPU_GCREGFETCHCONTROL_COUNT_MASK

#define GPU_GCREGFETCHCONTROL_COUNT_MASK   (0x1FFFFFUL)

◆ GPU_GCREGFETCHCONTROL_COUNT_SET

#define GPU_GCREGFETCHCONTROL_COUNT_SET (   x)    (((uint32_t)(x) << GPU_GCREGFETCHCONTROL_COUNT_SHIFT) & GPU_GCREGFETCHCONTROL_COUNT_MASK)

◆ GPU_GCREGFETCHCONTROL_COUNT_SHIFT

#define GPU_GCREGFETCHCONTROL_COUNT_SHIFT   (0U)

◆ GPU_GCREGHICHIPPATCHREV_PATCH_REV_GET

#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_GET (   x)    (((uint32_t)(x) & GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK) >> GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT)

◆ GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK

#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK   (0xFFU)

◆ GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT

#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT   (0U)