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Data Structures | |
| struct | LVB_Type |
| #define LVB_CTRL_CH0_BIT_MAPPING_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_CH0_BIT_MAPPING_MASK) >> LVB_CTRL_CH0_BIT_MAPPING_SHIFT) |
| #define LVB_CTRL_CH0_BIT_MAPPING_MASK (0x20U) |
| #define LVB_CTRL_CH0_BIT_MAPPING_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_CH0_BIT_MAPPING_SHIFT) & LVB_CTRL_CH0_BIT_MAPPING_MASK) |
| #define LVB_CTRL_CH0_BIT_MAPPING_SHIFT (5U) |
| #define LVB_CTRL_CH0_EN_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_CH0_EN_MASK) >> LVB_CTRL_CH0_EN_SHIFT) |
| #define LVB_CTRL_CH0_EN_MASK (0x1U) |
| #define LVB_CTRL_CH0_EN_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_CH0_EN_SHIFT) & LVB_CTRL_CH0_EN_MASK) |
| #define LVB_CTRL_CH0_EN_SHIFT (0U) |
| #define LVB_CTRL_CH0_SEL_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_CH0_SEL_MASK) >> LVB_CTRL_CH0_SEL_SHIFT) |
| #define LVB_CTRL_CH0_SEL_MASK (0x2U) |
| #define LVB_CTRL_CH0_SEL_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_CH0_SEL_SHIFT) & LVB_CTRL_CH0_SEL_MASK) |
| #define LVB_CTRL_CH0_SEL_SHIFT (1U) |
| #define LVB_CTRL_CH1_BIT_MAPPING_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_CH1_BIT_MAPPING_MASK) >> LVB_CTRL_CH1_BIT_MAPPING_SHIFT) |
| #define LVB_CTRL_CH1_BIT_MAPPING_MASK (0x80U) |
| #define LVB_CTRL_CH1_BIT_MAPPING_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_CH1_BIT_MAPPING_SHIFT) & LVB_CTRL_CH1_BIT_MAPPING_MASK) |
| #define LVB_CTRL_CH1_BIT_MAPPING_SHIFT (7U) |
| #define LVB_CTRL_CH1_EN_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_CH1_EN_MASK) >> LVB_CTRL_CH1_EN_SHIFT) |
| #define LVB_CTRL_CH1_EN_MASK (0x4U) |
| #define LVB_CTRL_CH1_EN_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_CH1_EN_SHIFT) & LVB_CTRL_CH1_EN_MASK) |
| #define LVB_CTRL_CH1_EN_SHIFT (2U) |
| #define LVB_CTRL_CH1_SEL_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_CH1_SEL_MASK) >> LVB_CTRL_CH1_SEL_SHIFT) |
| #define LVB_CTRL_CH1_SEL_MASK (0x8U) |
| #define LVB_CTRL_CH1_SEL_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_CH1_SEL_SHIFT) & LVB_CTRL_CH1_SEL_MASK) |
| #define LVB_CTRL_CH1_SEL_SHIFT (3U) |
| #define LVB_CTRL_DI0_VSYNC_POLARITY_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_DI0_VSYNC_POLARITY_MASK) >> LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT) |
| #define LVB_CTRL_DI0_VSYNC_POLARITY_MASK (0x10000UL) |
| #define LVB_CTRL_DI0_VSYNC_POLARITY_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT) & LVB_CTRL_DI0_VSYNC_POLARITY_MASK) |
| #define LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT (16U) |
| #define LVB_CTRL_DI1_VSYNC_POLARITY_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_DI1_VSYNC_POLARITY_MASK) >> LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT) |
| #define LVB_CTRL_DI1_VSYNC_POLARITY_MASK (0x20000UL) |
| #define LVB_CTRL_DI1_VSYNC_POLARITY_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT) & LVB_CTRL_DI1_VSYNC_POLARITY_MASK) |
| #define LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT (17U) |
| #define LVB_CTRL_LVDS_TXCLK_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_LVDS_TXCLK_SHIFT_MASK) >> LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT) |
| #define LVB_CTRL_LVDS_TXCLK_SHIFT_MASK (0x700U) |
| #define LVB_CTRL_LVDS_TXCLK_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT) & LVB_CTRL_LVDS_TXCLK_SHIFT_MASK) |
| #define LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT (8U) |
| #define LVB_CTRL_SPLIT_CH_MODE_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_SPLIT_CH_MODE_MASK) >> LVB_CTRL_SPLIT_CH_MODE_SHIFT) |
| #define LVB_CTRL_SPLIT_CH_MODE_MASK (0x4000000UL) |
| #define LVB_CTRL_SPLIT_CH_MODE_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_SPLIT_CH_MODE_SHIFT) & LVB_CTRL_SPLIT_CH_MODE_MASK) |
| #define LVB_CTRL_SPLIT_CH_MODE_SHIFT (26U) |
| #define LVB_CTRL_SPLIT_CH_REVERSE_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_SPLIT_CH_REVERSE_MASK) >> LVB_CTRL_SPLIT_CH_REVERSE_SHIFT) |
| #define LVB_CTRL_SPLIT_CH_REVERSE_MASK (0x8000000UL) |
| #define LVB_CTRL_SPLIT_CH_REVERSE_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_SPLIT_CH_REVERSE_SHIFT) & LVB_CTRL_SPLIT_CH_REVERSE_MASK) |
| #define LVB_CTRL_SPLIT_CH_REVERSE_SHIFT (27U) |
| #define LVB_CTRL_SPLIT_HSWHBP_WIDTH_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK) >> LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT) |
| #define LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK (0x2000000UL) |
| #define LVB_CTRL_SPLIT_HSWHBP_WIDTH_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT) & LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK) |
| #define LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT (25U) |
| #define LVB_CTRL_SPLIT_MODE_EN_GET | ( | x | ) | (((uint32_t)(x) & LVB_CTRL_SPLIT_MODE_EN_MASK) >> LVB_CTRL_SPLIT_MODE_EN_SHIFT) |
| #define LVB_CTRL_SPLIT_MODE_EN_MASK (0x1000000UL) |
| #define LVB_CTRL_SPLIT_MODE_EN_SET | ( | x | ) | (((uint32_t)(x) << LVB_CTRL_SPLIT_MODE_EN_SHIFT) & LVB_CTRL_SPLIT_MODE_EN_MASK) |
| #define LVB_CTRL_SPLIT_MODE_EN_SHIFT (24U) |
| #define LVB_PHY_POW_CTRL_LVDS0 (0UL) |
| #define LVB_PHY_POW_CTRL_LVDS1 (1UL) |
| #define LVB_PHY_POW_CTRL_PWON_PLL_GET | ( | x | ) | (((uint32_t)(x) & LVB_PHY_POW_CTRL_PWON_PLL_MASK) >> LVB_PHY_POW_CTRL_PWON_PLL_SHIFT) |
| #define LVB_PHY_POW_CTRL_PWON_PLL_MASK (0x20U) |
| #define LVB_PHY_POW_CTRL_PWON_PLL_SET | ( | x | ) | (((uint32_t)(x) << LVB_PHY_POW_CTRL_PWON_PLL_SHIFT) & LVB_PHY_POW_CTRL_PWON_PLL_MASK) |
| #define LVB_PHY_POW_CTRL_PWON_PLL_SHIFT (5U) |
| #define LVB_PHY_POW_CTRL_TX0_PD_GET | ( | x | ) | (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX0_PD_MASK) >> LVB_PHY_POW_CTRL_TX0_PD_SHIFT) |
| #define LVB_PHY_POW_CTRL_TX0_PD_MASK (0x1U) |
| #define LVB_PHY_POW_CTRL_TX0_PD_SET | ( | x | ) | (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX0_PD_SHIFT) & LVB_PHY_POW_CTRL_TX0_PD_MASK) |
| #define LVB_PHY_POW_CTRL_TX0_PD_SHIFT (0U) |
| #define LVB_PHY_POW_CTRL_TX1_PD_GET | ( | x | ) | (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX1_PD_MASK) >> LVB_PHY_POW_CTRL_TX1_PD_SHIFT) |
| #define LVB_PHY_POW_CTRL_TX1_PD_MASK (0x2U) |
| #define LVB_PHY_POW_CTRL_TX1_PD_SET | ( | x | ) | (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX1_PD_SHIFT) & LVB_PHY_POW_CTRL_TX1_PD_MASK) |
| #define LVB_PHY_POW_CTRL_TX1_PD_SHIFT (1U) |
| #define LVB_PHY_POW_CTRL_TX2_PD_GET | ( | x | ) | (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX2_PD_MASK) >> LVB_PHY_POW_CTRL_TX2_PD_SHIFT) |
| #define LVB_PHY_POW_CTRL_TX2_PD_MASK (0x4U) |
| #define LVB_PHY_POW_CTRL_TX2_PD_SET | ( | x | ) | (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX2_PD_SHIFT) & LVB_PHY_POW_CTRL_TX2_PD_MASK) |
| #define LVB_PHY_POW_CTRL_TX2_PD_SHIFT (2U) |
| #define LVB_PHY_POW_CTRL_TX3_PD_GET | ( | x | ) | (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX3_PD_MASK) >> LVB_PHY_POW_CTRL_TX3_PD_SHIFT) |
| #define LVB_PHY_POW_CTRL_TX3_PD_MASK (0x8U) |
| #define LVB_PHY_POW_CTRL_TX3_PD_SET | ( | x | ) | (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX3_PD_SHIFT) & LVB_PHY_POW_CTRL_TX3_PD_MASK) |
| #define LVB_PHY_POW_CTRL_TX3_PD_SHIFT (3U) |
| #define LVB_PHY_POW_CTRL_TXCK_PD_GET | ( | x | ) | (((uint32_t)(x) & LVB_PHY_POW_CTRL_TXCK_PD_MASK) >> LVB_PHY_POW_CTRL_TXCK_PD_SHIFT) |
| #define LVB_PHY_POW_CTRL_TXCK_PD_MASK (0x10U) |
| #define LVB_PHY_POW_CTRL_TXCK_PD_SET | ( | x | ) | (((uint32_t)(x) << LVB_PHY_POW_CTRL_TXCK_PD_SHIFT) & LVB_PHY_POW_CTRL_TXCK_PD_MASK) |
| #define LVB_PHY_POW_CTRL_TXCK_PD_SHIFT (4U) |
| #define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_GET | ( | x | ) | (((uint32_t)(x) & LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_MASK) >> LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_SHIFT) |
| #define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_MASK (0x1U) |
| #define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_SHIFT (0U) |
| #define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_GET | ( | x | ) | (((uint32_t)(x) & LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_MASK) >> LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_SHIFT) |
| #define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_MASK (0x2U) |
| #define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_SHIFT (1U) |
| #define LVB_TX_PHY_CTL0_TX_AMP_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_AMP_MASK) >> LVB_TX_PHY_CTL0_TX_AMP_SHIFT) |
| #define LVB_TX_PHY_CTL0_TX_AMP_MASK (0xF0U) |
| #define LVB_TX_PHY_CTL0_TX_AMP_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_AMP_SHIFT) & LVB_TX_PHY_CTL0_TX_AMP_MASK) |
| #define LVB_TX_PHY_CTL0_TX_AMP_SHIFT (4U) |
| #define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK) >> LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT) |
| #define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK (0x70000UL) |
| #define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT) & LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK) |
| #define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT (16U) |
| #define LVB_TX_PHY_CTL0_TX_DEEMP_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_DEEMP_MASK) >> LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT) |
| #define LVB_TX_PHY_CTL0_TX_DEEMP_MASK (0x3U) |
| #define LVB_TX_PHY_CTL0_TX_DEEMP_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT) & LVB_TX_PHY_CTL0_TX_DEEMP_MASK) |
| #define LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT (0U) |
| #define LVB_TX_PHY_CTL0_TX_IDLE_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_IDLE_MASK) >> LVB_TX_PHY_CTL0_TX_IDLE_SHIFT) |
| #define LVB_TX_PHY_CTL0_TX_IDLE_MASK (0x100000UL) |
| #define LVB_TX_PHY_CTL0_TX_IDLE_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_IDLE_SHIFT) & LVB_TX_PHY_CTL0_TX_IDLE_MASK) |
| #define LVB_TX_PHY_CTL0_TX_IDLE_SHIFT (20U) |
| #define LVB_TX_PHY_CTL0_TX_PHASE_SEL_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK) >> LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT) |
| #define LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK (0xF000U) |
| #define LVB_TX_PHY_CTL0_TX_PHASE_SEL_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT) & LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK) |
| #define LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT (12U) |
| #define LVB_TX_PHY_CTL0_TX_RTERM_EN_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK) >> LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT) |
| #define LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK (0x80000UL) |
| #define LVB_TX_PHY_CTL0_TX_RTERM_EN_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT) & LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK) |
| #define LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT (19U) |
| #define LVB_TX_PHY_CTL0_TX_SR_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_SR_MASK) >> LVB_TX_PHY_CTL0_TX_SR_SHIFT) |
| #define LVB_TX_PHY_CTL0_TX_SR_MASK (0xCU) |
| #define LVB_TX_PHY_CTL0_TX_SR_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_SR_SHIFT) & LVB_TX_PHY_CTL0_TX_SR_MASK) |
| #define LVB_TX_PHY_CTL0_TX_SR_SHIFT (2U) |
| #define LVB_TX_PHY_CTL0_TX_VCOM_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_VCOM_MASK) >> LVB_TX_PHY_CTL0_TX_VCOM_SHIFT) |
| #define LVB_TX_PHY_CTL0_TX_VCOM_MASK (0xF00U) |
| #define LVB_TX_PHY_CTL0_TX_VCOM_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_VCOM_SHIFT) & LVB_TX_PHY_CTL0_TX_VCOM_MASK) |
| #define LVB_TX_PHY_CTL0_TX_VCOM_SHIFT (8U) |
| #define LVB_TX_PHY_CTL1_TX_CTL_GET | ( | x | ) | (((uint32_t)(x) & LVB_TX_PHY_CTL1_TX_CTL_MASK) >> LVB_TX_PHY_CTL1_TX_CTL_SHIFT) |
| #define LVB_TX_PHY_CTL1_TX_CTL_MASK (0xFFFFFUL) |
| #define LVB_TX_PHY_CTL1_TX_CTL_SET | ( | x | ) | (((uint32_t)(x) << LVB_TX_PHY_CTL1_TX_CTL_SHIFT) & LVB_TX_PHY_CTL1_TX_CTL_MASK) |
| #define LVB_TX_PHY_CTL1_TX_CTL_SHIFT (0U) |
| #define LVB_TX_PHY_LVDS0_TX0 (0UL) |
| #define LVB_TX_PHY_LVDS0_TX1 (1UL) |
| #define LVB_TX_PHY_LVDS0_TX2 (1UL) |
| #define LVB_TX_PHY_LVDS0_TX3 (3UL) |
| #define LVB_TX_PHY_LVDS0_TXCK (4UL) |
| #define LVB_TX_PHY_LVDS1_TX0 (5UL) |
| #define LVB_TX_PHY_LVDS1_TX1 (6UL) |
| #define LVB_TX_PHY_LVDS1_TX2 (7UL) |
| #define LVB_TX_PHY_LVDS1_TX3 (8UL) |
| #define LVB_TX_PHY_LVDS1_TXCK (9UL) |