Data Structures
struct	MIPI_DSI_Type

Macros
#define	MIPI_DSI_VERSION_VERSION_MASK (0xFFFFFFFFUL)

#define	MIPI_DSI_VERSION_VERSION_SHIFT (0U)

#define	MIPI_DSI_VERSION_VERSION_GET(x) (((uint32_t)(x) & MIPI_DSI_VERSION_VERSION_MASK) >> MIPI_DSI_VERSION_VERSION_SHIFT)

#define	MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK (0x1U)

#define	MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT (0U)

#define	MIPI_DSI_PWR_UP_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK)

#define	MIPI_DSI_PWR_UP_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) >> MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT)

#define	MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK (0xFF00U)

#define	MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT (8U)

#define	MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK)

#define	MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT)

#define	MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK (0xFFU)

#define	MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT (0U)

#define	MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK)

#define	MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT)

#define	MIPI_DSI_DPI_VCID_DPI_VCID_MASK (0x3U)

#define	MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT (0U)

#define	MIPI_DSI_DPI_VCID_DPI_VCID_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK)

#define	MIPI_DSI_DPI_VCID_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT)

#define	MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK (0x100U)

#define	MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT (8U)

#define	MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK)

#define	MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT)

#define	MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK (0xFU)

#define	MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT (0U)

#define	MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK)

#define	MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT)

#define	MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK (0x10U)

#define	MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT (4U)

#define	MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK)

#define	MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT)

#define	MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK (0x8U)

#define	MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT (3U)

#define	MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK)

#define	MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT)

#define	MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK (0x4U)

#define	MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT (2U)

#define	MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK)

#define	MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT)

#define	MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK (0x2U)

#define	MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT (1U)

#define	MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK)

#define	MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT)

#define	MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK (0x1U)

#define	MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT (0U)

#define	MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK)

#define	MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT)

#define	MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL)

#define	MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT (16U)

#define	MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK)

#define	MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT)

#define	MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK (0xFFU)

#define	MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT (0U)

#define	MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK)

#define	MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK (0x20U)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT (5U)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT)

#define	MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK (0x10U)

#define	MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT (4U)

#define	MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK)

#define	MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT)

#define	MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK (0x8U)

#define	MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT (3U)

#define	MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK)

#define	MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT)

#define	MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK (0x4U)

#define	MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT (2U)

#define	MIPI_DSI_PCKHDL_CFG_BTA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK)

#define	MIPI_DSI_PCKHDL_CFG_BTA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK (0x2U)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT (1U)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK (0x1U)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT (0U)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK)

#define	MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK (0x30000UL)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT (16U)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK (0x300U)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT (8U)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK (0x3U)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT (0U)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_RX_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK)

#define	MIPI_DSI_GEN_VCID_GEN_VCID_RX_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT)

#define	MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK (0x1U)

#define	MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT (0U)

#define	MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK)

#define	MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) >> MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK (0x1000000UL)

#define	MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT (24U)

#define	MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK)

#define	MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK (0x100000UL)

#define	MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT (20U)

#define	MIPI_DSI_VID_MODE_CFG_VPG_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK)

#define	MIPI_DSI_VID_MODE_CFG_VPG_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK (0x10000UL)

#define	MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT (16U)

#define	MIPI_DSI_VID_MODE_CFG_VPG_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_VPG_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK (0x8000U)

#define	MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT (15U)

#define	MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK (0x4000U)

#define	MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT (14U)

#define	MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK (0x2000U)

#define	MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT (13U)

#define	MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK (0x1000U)

#define	MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT (12U)

#define	MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK (0x800U)

#define	MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT (11U)

#define	MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK (0x400U)

#define	MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT (10U)

#define	MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK (0x200U)

#define	MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT (9U)

#define	MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK (0x100U)

#define	MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT (8U)

#define	MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK)

#define	MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK (0x3U)

#define	MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT (0U)

#define	MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK)

#define	MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT)

#define	MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK (0x3FFFU)

#define	MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT (0U)

#define	MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK)

#define	MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT)

#define	MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK (0x1FFFU)

#define	MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT (0U)

#define	MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK)

#define	MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT)

#define	MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK (0x1FFFU)

#define	MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT (0U)

#define	MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK)

#define	MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT)

#define	MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK (0xFFFU)

#define	MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT (0U)

#define	MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK)

#define	MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT)

#define	MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK (0xFFFU)

#define	MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT (0U)

#define	MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK)

#define	MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT)

#define	MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK (0x7FFFU)

#define	MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT (0U)

#define	MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK)

#define	MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT)

#define	MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK (0x3FFU)

#define	MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT (0U)

#define	MIPI_DSI_VID_VSA_LINES_VSA_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK)

#define	MIPI_DSI_VID_VSA_LINES_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT)

#define	MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK (0x3FFU)

#define	MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT (0U)

#define	MIPI_DSI_VID_VBP_LINES_VBP_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK)

#define	MIPI_DSI_VID_VBP_LINES_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT)

#define	MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK (0x3FFU)

#define	MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT (0U)

#define	MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK)

#define	MIPI_DSI_VID_VFP_LINES_VFP_LINIES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) >> MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT)

#define	MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK (0x3FFFU)

#define	MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT (0U)

#define	MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK)

#define	MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK (0x1000000UL)

#define	MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT (24U)

#define	MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) >> MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK (0x80000UL)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT (19U)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK (0x40000UL)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT (18U)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK (0x20000UL)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT (17U)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK (0x10000UL)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT (16U)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK (0x4000U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT (14U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK (0x2000U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT (13U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK (0x1000U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT (12U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK (0x800U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT (11U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK (0x400U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT (10U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK (0x200U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT (9U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK (0x100U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT (8U)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK (0x2U)

#define	MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT (1U)

#define	MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT)

#define	MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK (0x1U)

#define	MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT (0U)

#define	MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK)

#define	MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT)

#define	MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK (0xFF0000UL)

#define	MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT (16U)

#define	MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK)

#define	MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT)

#define	MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK (0xFF00U)

#define	MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT (8U)

#define	MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK)

#define	MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT)

#define	MIPI_DSI_GEN_HDR_GEN_VC_MASK (0xC0U)

#define	MIPI_DSI_GEN_HDR_GEN_VC_SHIFT (6U)

#define	MIPI_DSI_GEN_HDR_GEN_VC_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) & MIPI_DSI_GEN_HDR_GEN_VC_MASK)

#define	MIPI_DSI_GEN_HDR_GEN_VC_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) >> MIPI_DSI_GEN_HDR_GEN_VC_SHIFT)

#define	MIPI_DSI_GEN_HDR_GEN_DT_MASK (0x3FU)

#define	MIPI_DSI_GEN_HDR_GEN_DT_SHIFT (0U)

#define	MIPI_DSI_GEN_HDR_GEN_DT_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) & MIPI_DSI_GEN_HDR_GEN_DT_MASK)

#define	MIPI_DSI_GEN_HDR_GEN_DT_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) >> MIPI_DSI_GEN_HDR_GEN_DT_SHIFT)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK (0xFF000000UL)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT (24U)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK (0xFF0000UL)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT (16U)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK (0xFF00U)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT (8U)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK (0xFFU)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT (0U)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK)

#define	MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK (0x80000UL)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT (19U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK (0x40000UL)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT (18U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK (0x20000UL)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT (17U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK (0x10000UL)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT (16U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK (0x40U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT (6U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK (0x20U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT (5U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK (0x10U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT (4U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK (0x8U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT (3U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK (0x4U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT (2U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK (0x2U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT (1U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK (0x1U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT (0U)

#define	MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT)

#define	MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK (0xFFFF0000UL)

#define	MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT (16U)

#define	MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK)

#define	MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT)

#define	MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK (0xFFFFU)

#define	MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT (0U)

#define	MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK)

#define	MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT)

#define	MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK (0xFFFFU)

#define	MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT (0U)

#define	MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK)

#define	MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) >> MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT)

#define	MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK (0xFFFFU)

#define	MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT (0U)

#define	MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK)

#define	MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) >> MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT)

#define	MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK (0xFFFFU)

#define	MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT (0U)

#define	MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK)

#define	MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) >> MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT)

#define	MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK (0xFFFFU)

#define	MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT (0U)

#define	MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK)

#define	MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) >> MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT)

#define	MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK (0xFFFFU)

#define	MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT (0U)

#define	MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK)

#define	MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) >> MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT)

#define	MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK (0x10000UL)

#define	MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT (16U)

#define	MIPI_DSI_SDF_3D_SEND_3D_CFG_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK)

#define	MIPI_DSI_SDF_3D_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT)

#define	MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK (0x20U)

#define	MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT (5U)

#define	MIPI_DSI_SDF_3D_RIGHT_FIRST_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK)

#define	MIPI_DSI_SDF_3D_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT)

#define	MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK (0x10U)

#define	MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT (4U)

#define	MIPI_DSI_SDF_3D_SECOND_VSYNC_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK)

#define	MIPI_DSI_SDF_3D_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT)

#define	MIPI_DSI_SDF_3D_FORMAT_3D_MASK (0xCU)

#define	MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT (2U)

#define	MIPI_DSI_SDF_3D_FORMAT_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK)

#define	MIPI_DSI_SDF_3D_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT)

#define	MIPI_DSI_SDF_3D_MODE_3D_MASK (0x3U)

#define	MIPI_DSI_SDF_3D_MODE_3D_SHIFT (0U)

#define	MIPI_DSI_SDF_3D_MODE_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_MODE_3D_SHIFT) & MIPI_DSI_SDF_3D_MODE_3D_MASK)

#define	MIPI_DSI_SDF_3D_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_MODE_3D_SHIFT)

#define	MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK (0x2U)

#define	MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT (1U)

#define	MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK)

#define	MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) >> MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT)

#define	MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK (0x1U)

#define	MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT (0U)

#define	MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK)

#define	MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) >> MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT)

#define	MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK (0x3FF0000UL)

#define	MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT (16U)

#define	MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK)

#define	MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT)

#define	MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK (0x3FFU)

#define	MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT (0U)

#define	MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK)

#define	MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT)

#define	MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK (0x3FF0000UL)

#define	MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT (16U)

#define	MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK)

#define	MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT)

#define	MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK (0x3FFU)

#define	MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT (0U)

#define	MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK)

#define	MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT)

#define	MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK (0x8U)

#define	MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT (3U)

#define	MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK)

#define	MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT)

#define	MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK (0x4U)

#define	MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT (2U)

#define	MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK)

#define	MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT)

#define	MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK (0x2U)

#define	MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT (1U)

#define	MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK)

#define	MIPI_DSI_PHY_RSTZ_PHY_RSTZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT)

#define	MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK (0x1U)

#define	MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT (0U)

#define	MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK)

#define	MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT)

#define	MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK (0xFF00U)

#define	MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT (8U)

#define	MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK)

#define	MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) >> MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT)

#define	MIPI_DSI_PHY_IF_CFG_N_LANES_MASK (0x3U)

#define	MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT (0U)

#define	MIPI_DSI_PHY_IF_CFG_N_LANES_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK)

#define	MIPI_DSI_PHY_IF_CFG_N_LANES_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) >> MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK (0x8U)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT (3U)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK (0x4U)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT (2U)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK (0x2U)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT (1U)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK (0x1U)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT (0U)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK)

#define	MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT)

#define	MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK (0xFU)

#define	MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT (0U)

#define	MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK)

#define	MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) >> MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK (0x1000U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT (12U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK (0x800U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT (11U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK (0x400U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT (10U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK (0x200U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT (9U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK (0x100U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT (8U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK (0x80U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT (7U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK (0x40U)

#define	MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT (6U)

#define	MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK (0x20U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT (5U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK (0x10U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT (4U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK (0x8U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT (3U)

#define	MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK (0x4U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT (2U)

#define	MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK (0x2U)

#define	MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT (1U)

#define	MIPI_DSI_PHY_STATUS_PHY_DIRECTION_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK) >> MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT)

#define	MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK (0x1U)

#define	MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT (0U)

#define	MIPI_DSI_PHY_STATUS_PHY_LOCK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT)

#define	MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK (0x2U)

#define	MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT (1U)

#define	MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK)

#define	MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT)

#define	MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK (0x1U)

#define	MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT (0U)

#define	MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK)

#define	MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK (0x10000UL)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT (16U)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK (0xFF00U)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT (8U)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK (0xFFU)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT (0U)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK)

#define	MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK (0x100000UL)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT (20U)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK (0x80000UL)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT (19U)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK (0x40000UL)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT (18U)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK (0x20000UL)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT (17U)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK (0x10000UL)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT (16U)

#define	MIPI_DSI_INT_ST0_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK (0x8000U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT (15U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK (0x4000U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT (14U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK (0x2000U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT (13U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK (0x1000U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT (12U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK (0x800U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT (11U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK (0x400U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT (10U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK (0x200U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT (9U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK (0x100U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT (8U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK (0x80U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT (7U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK (0x40U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT (6U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK (0x20U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT (5U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK (0x10U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT (4U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK (0x8U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT (3U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK (0x4U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT (2U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK (0x2U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT (1U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK (0x1U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT (0U)

#define	MIPI_DSI_INT_ST0_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT)

#define	MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK (0x100000UL)

#define	MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT (20U)

#define	MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK (0x80000UL)

#define	MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT (19U)

#define	MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT)

#define	MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK (0x1000U)

#define	MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT (12U)

#define	MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK (0x800U)

#define	MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT (11U)

#define	MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK (0x400U)

#define	MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT (10U)

#define	MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK (0x200U)

#define	MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT (9U)

#define	MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK (0x100U)

#define	MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT (8U)

#define	MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK (0x80U)

#define	MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT (7U)

#define	MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_EOPT_ERR_MASK (0x40U)

#define	MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT (6U)

#define	MIPI_DSI_INT_ST1_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_EOPT_ERR_MASK) >> MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK (0x20U)

#define	MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT (5U)

#define	MIPI_DSI_INT_ST1_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_CRC_ERR_MASK (0x10U)

#define	MIPI_DSI_INT_ST1_CRC_ERR_SHIFT (4U)

#define	MIPI_DSI_INT_ST1_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_CRC_ERR_MASK) >> MIPI_DSI_INT_ST1_CRC_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK (0x8U)

#define	MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT (3U)

#define	MIPI_DSI_INT_ST1_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK (0x4U)

#define	MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT (2U)

#define	MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT)

#define	MIPI_DSI_INT_ST1_TO_LP_TX_MASK (0x2U)

#define	MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT (1U)

#define	MIPI_DSI_INT_ST1_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_LP_TX_MASK) >> MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT)

#define	MIPI_DSI_INT_ST1_TO_HS_TX_MASK (0x1U)

#define	MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT (0U)

#define	MIPI_DSI_INT_ST1_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_HS_TX_MASK) >> MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK (0x100000UL)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT (20U)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK (0x80000UL)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT (19U)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK (0x40000UL)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT (18U)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK (0x20000UL)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT (17U)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK (0x10000UL)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT (16U)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK (0x8000U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT (15U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK (0x4000U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT (14U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK (0x2000U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT (13U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK (0x1000U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT (12U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK (0x800U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT (11U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK (0x400U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT (10U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK (0x200U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT (9U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK (0x100U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT (8U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK (0x80U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT (7U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK (0x40U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT (6U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK (0x20U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT (5U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK (0x10U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT (4U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK (0x8U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT (3U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK (0x4U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT (2U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK (0x2U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT (1U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK (0x1U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT (0U)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK)

#define	MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK (0x100000UL)

#define	MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT (20U)

#define	MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK (0x80000UL)

#define	MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT (19U)

#define	MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK (0x1000U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT (12U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK (0x800U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT (11U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK (0x400U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT (10U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK (0x200U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT (9U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK (0x100U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT (8U)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK (0x80U)

#define	MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT (7U)

#define	MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK (0x40U)

#define	MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT (6U)

#define	MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK (0x20U)

#define	MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT (5U)

#define	MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK (0x10U)

#define	MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT (4U)

#define	MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK (0x8U)

#define	MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT (3U)

#define	MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK (0x4U)

#define	MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT (2U)

#define	MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK (0x2U)

#define	MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT (1U)

#define	MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT)

#define	MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK (0x1U)

#define	MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT (0U)

#define	MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK)

#define	MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT)

#define	MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK (0x1U)

#define	MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT (0U)

#define	MIPI_DSI_PHY_CAL_TXSKEWCALHS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK)

#define	MIPI_DSI_PHY_CAL_TXSKEWCALHS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) >> MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK (0x100000UL)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT (20U)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK (0x80000UL)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT (19U)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK (0x40000UL)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT (18U)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK (0x20000UL)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT (17U)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK (0x10000UL)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT (16U)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK (0x8000U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT (15U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK (0x4000U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT (14U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK (0x2000U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT (13U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK (0x1000U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT (12U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK (0x800U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT (11U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK (0x400U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT (10U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK (0x200U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT (9U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK (0x100U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT (8U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK (0x80U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT (7U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK (0x40U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT (6U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK (0x20U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT (5U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK (0x10U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT (4U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK (0x8U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT (3U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK (0x4U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT (2U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK (0x2U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT (1U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK (0x1U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT (0U)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK)

#define	MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK (0x100000UL)

#define	MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT (20U)

#define	MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK (0x80000UL)

#define	MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT (19U)

#define	MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK (0x1000U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT (12U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK (0x800U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT (11U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK (0x400U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT (10U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK (0x200U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT (9U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK (0x100U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT (8U)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK (0x80U)

#define	MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT (7U)

#define	MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK (0x40U)

#define	MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT (6U)

#define	MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK (0x20U)

#define	MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT (5U)

#define	MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK (0x10U)

#define	MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT (4U)

#define	MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK (0x8U)

#define	MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT (3U)

#define	MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK (0x4U)

#define	MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT (2U)

#define	MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK (0x2U)

#define	MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT (1U)

#define	MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT)

#define	MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK (0x1U)

#define	MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT (0U)

#define	MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK)

#define	MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT)

#define	MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK (0x7FFFU)

#define	MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT (0U)

#define	MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK)

#define	MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) >> MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT)

#define	MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK (0xFFFU)

#define	MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT (0U)

#define	MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK)

#define	MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) >> MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT)

#define	MIPI_DSI_PHY_MODE_PHY_MODE_MASK (0x1U)

#define	MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT (0U)

#define	MIPI_DSI_PHY_MODE_PHY_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK)

#define	MIPI_DSI_PHY_MODE_PHY_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) >> MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK (0x10000UL)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT (16U)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK (0x100U)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT (8U)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK (0x1U)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT (0U)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK)

#define	MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT)

#define	MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK (0x3U)

#define	MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT (0U)

#define	MIPI_DSI_DPI_VCID_ACT_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT)

#define	MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK (0x100U)

#define	MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT (8U)

#define	MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT)

#define	MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK (0xFU)

#define	MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT (0U)

#define	MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT)

#define	MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL)

#define	MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT (16U)

#define	MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT)

#define	MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK (0xFFU)

#define	MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT (0U)

#define	MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK (0x200U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT (9U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK (0x100U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT (8U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK (0x80U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT (7U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK (0x40U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT (6U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK (0x20U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT (5U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK (0x10U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT (4U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK (0x8U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT (3U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK (0x4U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT (2U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT)

#define	MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK (0x3U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT (0U)

#define	MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT)

#define	MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK (0x3FFFU)

#define	MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT (0U)

#define	MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT)

#define	MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK (0x1FFFU)

#define	MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT (0U)

#define	MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT)

#define	MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK (0x1FFFU)

#define	MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT (0U)

#define	MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT)

#define	MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK (0xFFFU)

#define	MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT (0U)

#define	MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT)

#define	MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK (0xFFFU)

#define	MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT (0U)

#define	MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT)

#define	MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK (0x7FFFU)

#define	MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT (0U)

#define	MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT)

#define	MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK (0x3FFU)

#define	MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT (0U)

#define	MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT)

#define	MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK (0x3FFU)

#define	MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT (0U)

#define	MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT)

#define	MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK (0x3FFU)

#define	MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT (0U)

#define	MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK) >> MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT)

#define	MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK (0x3FFFU)

#define	MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT (0U)

#define	MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK (0x20000UL)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT (17U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK (0x10000UL)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT (16U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK (0x8U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT (3U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK (0x4U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT (2U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK (0x2U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT (1U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK (0x1U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT (0U)

#define	MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT)

#define	MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK (0x10000UL)

#define	MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT (16U)

#define	MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT)

#define	MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK (0x20U)

#define	MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT (5U)

#define	MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT)

#define	MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK (0x10U)

#define	MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT (4U)

#define	MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT)

#define	MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK (0xCU)

#define	MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT (2U)

#define	MIPI_DSI_SDF_3D_ACT_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT)

#define	MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK (0x3U)

#define	MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT (0U)

#define	MIPI_DSI_SDF_3D_ACT_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT)

Macro Definition Documentation

◆ MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_GET

#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) >> MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT)

◆ MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK

#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK (0xFFFU)

◆ MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SET

#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK)

◆ MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT

#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT (0U)

◆ MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_GET

#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) >> MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT)

◆ MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK

#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK (0xFFFFU)

◆ MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET

#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET ( x ) (((uint32_t)(x) << MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK)

◆ MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT

#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT (0U)

◆ MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_GET

#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT)

◆ MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK

#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK (0xFF00U)

◆ MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET

#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK)

◆ MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT

#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT (8U)

◆ MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_GET

#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT)

◆ MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK

#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK (0xFFU)

◆ MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET

#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK)

◆ MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT

#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT (0U)

◆ MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_GET

#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK

#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK (0x2U)

◆ MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SET

#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT (1U)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK (0x80000UL)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT (19U)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK (0x40000UL)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT (18U)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK (0x10000UL)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT (16U)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK (0x20000UL)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT (17U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK (0x4000U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT (14U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK (0x800U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT (11U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK (0x1000U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT (12U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK (0x2000U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT (13U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK (0x100U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT (8U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK (0x200U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT (9U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_GET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK (0x400U)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SET

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT (10U)

◆ MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_GET

#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) >> MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK

#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK (0x1000000UL)

◆ MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SET

#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT (24U)

◆ MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_GET

#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT)

◆ MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK

#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK (0x1U)

◆ MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SET

#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK)

◆ MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT

#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT (0U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK (0x10000UL)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT (16U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK (0x20000UL)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT (17U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK (0x40000UL)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT (18U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK (0x80000UL)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT (19U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK (0x1U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT (0U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK (0x2U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT (1U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK (0x10U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT (4U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK (0x20U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT (5U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK (0x4U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT (2U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK (0x8U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT (3U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_GET

#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK

#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK (0x40U)

◆ MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT

#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT (6U)

◆ MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_GET

#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT)

◆ MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK

#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK (0x10U)

◆ MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SET

#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK)

◆ MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT

#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT (4U)

◆ MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_GET

#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT)

◆ MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK

#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK (0x1U)

◆ MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SET

#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK)

◆ MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT

#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT (0U)

◆ MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_GET

#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT)

◆ MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK

#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK (0x4U)

◆ MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SET

#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK)

◆ MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT

#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT (2U)

◆ MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_GET

#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT)

◆ MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK

#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK (0x8U)

◆ MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SET

#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK)

◆ MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT

#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT (3U)

◆ MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_GET

#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT)

◆ MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK

#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK (0x2U)

◆ MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SET

#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK)

◆ MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT

#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT (1U)

◆ MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_GET

#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT)

◆ MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK

#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK (0xFU)

◆ MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT

#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT (0U)

◆ MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_GET

#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT)

◆ MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK

#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK (0x100U)

◆ MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT

#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT (8U)

◆ MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_GET

#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT)

◆ MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK

#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK (0xFU)

◆ MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET

#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK)

◆ MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT

#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT (0U)

◆ MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_GET

#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT)

◆ MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK

#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK (0x100U)

◆ MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SET

#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK)

◆ MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT

#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT (8U)

◆ MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_GET

#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT)

◆ MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK

#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK (0xFFU)

◆ MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT

#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT (0U)

◆ MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_GET

#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT)

◆ MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK

#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL)

◆ MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT

#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT (16U)

◆ MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_GET

#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT)

◆ MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK

#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK (0xFFU)

◆ MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SET

#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK)

◆ MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT

#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT (0U)

◆ MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_GET

#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT)

◆ MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK

#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL)

◆ MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET

#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK)

◆ MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT

#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT (16U)

◆ MIPI_DSI_DPI_VCID_ACT_DPI_VCID_GET

#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT)

◆ MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK

#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK (0x3U)

◆ MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT

#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT (0U)

◆ MIPI_DSI_DPI_VCID_DPI_VCID_GET

#define MIPI_DSI_DPI_VCID_DPI_VCID_GET ( x ) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT)

◆ MIPI_DSI_DPI_VCID_DPI_VCID_MASK

#define MIPI_DSI_DPI_VCID_DPI_VCID_MASK (0x3U)

◆ MIPI_DSI_DPI_VCID_DPI_VCID_SET

#define MIPI_DSI_DPI_VCID_DPI_VCID_SET ( x ) (((uint32_t)(x) << MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK)

◆ MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT

#define MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT (0U)

◆ MIPI_DSI_GEN_HDR_GEN_DT_GET

#define MIPI_DSI_GEN_HDR_GEN_DT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) >> MIPI_DSI_GEN_HDR_GEN_DT_SHIFT)

◆ MIPI_DSI_GEN_HDR_GEN_DT_MASK

#define MIPI_DSI_GEN_HDR_GEN_DT_MASK (0x3FU)

◆ MIPI_DSI_GEN_HDR_GEN_DT_SET

#define MIPI_DSI_GEN_HDR_GEN_DT_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) & MIPI_DSI_GEN_HDR_GEN_DT_MASK)

◆ MIPI_DSI_GEN_HDR_GEN_DT_SHIFT

#define MIPI_DSI_GEN_HDR_GEN_DT_SHIFT (0U)

◆ MIPI_DSI_GEN_HDR_GEN_VC_GET

#define MIPI_DSI_GEN_HDR_GEN_VC_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) >> MIPI_DSI_GEN_HDR_GEN_VC_SHIFT)

◆ MIPI_DSI_GEN_HDR_GEN_VC_MASK

#define MIPI_DSI_GEN_HDR_GEN_VC_MASK (0xC0U)

◆ MIPI_DSI_GEN_HDR_GEN_VC_SET

#define MIPI_DSI_GEN_HDR_GEN_VC_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) & MIPI_DSI_GEN_HDR_GEN_VC_MASK)

◆ MIPI_DSI_GEN_HDR_GEN_VC_SHIFT

#define MIPI_DSI_GEN_HDR_GEN_VC_SHIFT (6U)

◆ MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_GET

#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT)

◆ MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK

#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK (0xFF00U)

◆ MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SET

#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK)

◆ MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT

#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT (8U)

◆ MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_GET

#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT)

◆ MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK

#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK (0xFF0000UL)

◆ MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SET

#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK)

◆ MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT

#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT (16U)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_GET

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK (0xFFU)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SET

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT (0U)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_GET

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK (0xFF00U)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SET

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT (8U)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_GET

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK (0xFF0000UL)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SET

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT (16U)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_GET

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK (0xFF000000UL)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SET

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK)

◆ MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT

#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT (24U)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_RX_GET

#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK

#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK (0x3U)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_RX_SET

#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT

#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT (0U)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_GET

#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK

#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK (0x300U)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SET

#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT

#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT (8U)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_GET

#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_GET ( x ) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK

#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK (0x30000UL)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SET

#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SET ( x ) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK)

◆ MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT

#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT (16U)

◆ MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_GET

#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) >> MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT)

◆ MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK

#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK (0xFFFFU)

◆ MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SET

#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SET ( x ) (((uint32_t)(x) << MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK)

◆ MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT

#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT (0U)

◆ MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_GET

#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) >> MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT)

◆ MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK

#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK (0xFFFFU)

◆ MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SET

#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SET ( x ) (((uint32_t)(x) << MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK)

◆ MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT

#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT (0U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK (0x1U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT (0U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK (0x2U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT (1U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK (0x4U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT (2U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK (0x8U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT (3U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK (0x10U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT (4U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK (0x20U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT (5U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK (0x40U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT (6U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK (0x80U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT (7U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK (0x100U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT (8U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK (0x400U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT (10U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK (0x800U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT (11U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK (0x1000U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT (12U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK (0x2000U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT (13U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK (0x4000U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT (14U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK (0x8000U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT (15U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_GET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK (0x200U)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SET

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT (9U)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_GET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK (0x10000UL)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT (16U)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_GET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK (0x20000UL)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT (17U)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_GET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK (0x40000UL)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT (18U)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_GET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK (0x80000UL)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT (19U)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_GET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK (0x100000UL)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SET

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK)

◆ MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT

#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT (20U)

◆ MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK (0x10U)

◆ MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT (4U)

◆ MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK (0x80U)

◆ MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT (7U)

◆ MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_GET

#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK (0x80000UL)

◆ MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SET

#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT (19U)

◆ MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK (0x8U)

◆ MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT (3U)

◆ MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK (0x4U)

◆ MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT (2U)

◆ MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK (0x40U)

◆ MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT (6U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK (0x100U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT (8U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK (0x800U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT (11U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK (0x1000U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT (12U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK (0x400U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT (10U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK (0x200U)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT (9U)

◆ MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK (0x20U)

◆ MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT (5U)

◆ MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_GET

#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK (0x100000UL)

◆ MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SET

#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT (20U)

◆ MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_GET

#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK (0x1U)

◆ MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SET

#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT (0U)

◆ MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_GET

#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT)

◆ MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK

#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK (0x2U)

◆ MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SET

#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK)

◆ MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT

#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT (1U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK (0x1U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT (0U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK (0x2U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT (1U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK (0x4U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT (2U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK (0x8U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT (3U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK (0x10U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT (4U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK (0x20U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT (5U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK (0x40U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT (6U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK (0x80U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT (7U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK (0x100U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT (8U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK (0x400U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT (10U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK (0x800U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT (11U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK (0x1000U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT (12U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK (0x2000U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT (13U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK (0x4000U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT (14U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK (0x8000U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT (15U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_GET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK (0x200U)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SET

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT (9U)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_GET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK (0x10000UL)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT (16U)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_GET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK (0x20000UL)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT (17U)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_GET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK (0x40000UL)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT (18U)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_GET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK (0x80000UL)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT (19U)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_GET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK (0x100000UL)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SET

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK)

◆ MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT

#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT (20U)

◆ MIPI_DSI_INT_MSK1_MASK_CRC_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK (0x10U)

◆ MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT (4U)

◆ MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK (0x80U)

◆ MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT (7U)

◆ MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_GET

#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK

#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK (0x80000UL)

◆ MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SET

#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT (19U)

◆ MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK (0x8U)

◆ MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT (3U)

◆ MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK (0x4U)

◆ MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT (2U)

◆ MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK (0x40U)

◆ MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT (6U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK (0x100U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT (8U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK (0x800U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT (11U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK (0x1000U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT (12U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK (0x400U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT (10U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK (0x200U)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT (9U)

◆ MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK (0x20U)

◆ MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT (5U)

◆ MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_GET

#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK

#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK (0x100000UL)

◆ MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SET

#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT (20U)

◆ MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_GET

#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK

#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK (0x1U)

◆ MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SET

#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT (0U)

◆ MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_GET

#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT)

◆ MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK

#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK (0x2U)

◆ MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SET

#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SET ( x ) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK)

◆ MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT

#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT (1U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR0_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK (0x1U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT (0U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR1_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK (0x2U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT (1U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR2_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK (0x4U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT (2U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR3_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK (0x8U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT (3U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR4_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK (0x10U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT (4U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR5_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK (0x20U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT (5U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR6_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK (0x40U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT (6U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR7_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK (0x80U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT (7U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR8_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK (0x100U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT (8U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK (0x400U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT (10U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK (0x800U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT (11U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK (0x1000U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT (12U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK (0x2000U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT (13U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK (0x4000U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT (14U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK (0x8000U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT (15U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_GET

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK (0x200U)

◆ MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT

#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT (9U)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_0_GET

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK (0x10000UL)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT (16U)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_1_GET

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK (0x20000UL)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT (17U)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_2_GET

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK (0x40000UL)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT (18U)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_3_GET

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK (0x80000UL)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT (19U)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_4_GET

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK (0x100000UL)

◆ MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT

#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT (20U)

◆ MIPI_DSI_INT_ST1_CRC_ERR_GET

#define MIPI_DSI_INT_ST1_CRC_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_CRC_ERR_MASK) >> MIPI_DSI_INT_ST1_CRC_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_CRC_ERR_MASK

#define MIPI_DSI_INT_ST1_CRC_ERR_MASK (0x10U)

◆ MIPI_DSI_INT_ST1_CRC_ERR_SHIFT

#define MIPI_DSI_INT_ST1_CRC_ERR_SHIFT (4U)

◆ MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_GET

#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK

#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK (0x80U)

◆ MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT

#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT (7U)

◆ MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_GET

#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT)

◆ MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK

#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK (0x80000UL)

◆ MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT

#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT (19U)

◆ MIPI_DSI_INT_ST1_ECC_MULTI_ERR_GET

#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK

#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK (0x8U)

◆ MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT

#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT (3U)

◆ MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_GET

#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK

#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK (0x4U)

◆ MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT

#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT (2U)

◆ MIPI_DSI_INT_ST1_EOPT_ERR_GET

#define MIPI_DSI_INT_ST1_EOPT_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_EOPT_ERR_MASK) >> MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_EOPT_ERR_MASK

#define MIPI_DSI_INT_ST1_EOPT_ERR_MASK (0x40U)

◆ MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT

#define MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT (6U)

◆ MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_GET

#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK

#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK (0x100U)

◆ MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT

#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT (8U)

◆ MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_GET

#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK

#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK (0x800U)

◆ MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT

#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT (11U)

◆ MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_GET

#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK

#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK (0x1000U)

◆ MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT

#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT (12U)

◆ MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_GET

#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK

#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK (0x400U)

◆ MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT

#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT (10U)

◆ MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_GET

#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK

#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK (0x200U)

◆ MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT

#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT (9U)

◆ MIPI_DSI_INT_ST1_PKT_SIZE_ERR_GET

#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK

#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK (0x20U)

◆ MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT

#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT (5U)

◆ MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_GET

#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT)

◆ MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK

#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK (0x100000UL)

◆ MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT

#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT (20U)

◆ MIPI_DSI_INT_ST1_TO_HS_TX_GET

#define MIPI_DSI_INT_ST1_TO_HS_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_HS_TX_MASK) >> MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT)

◆ MIPI_DSI_INT_ST1_TO_HS_TX_MASK

#define MIPI_DSI_INT_ST1_TO_HS_TX_MASK (0x1U)

◆ MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT

#define MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT (0U)

◆ MIPI_DSI_INT_ST1_TO_LP_TX_GET

#define MIPI_DSI_INT_ST1_TO_LP_TX_GET ( x ) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_LP_TX_MASK) >> MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT)

◆ MIPI_DSI_INT_ST1_TO_LP_TX_MASK

#define MIPI_DSI_INT_ST1_TO_LP_TX_MASK (0x2U)

◆ MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT

#define MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT (1U)

◆ MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_GET

#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) >> MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT)

◆ MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK

#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK (0xFFFFU)

◆ MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SET

#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SET ( x ) (((uint32_t)(x) << MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK)

◆ MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT

#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT (0U)

◆ MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_GET

#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) >> MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT)

◆ MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK

#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK (0xFFFFU)

◆ MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SET

#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SET ( x ) (((uint32_t)(x) << MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK)

◆ MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT

#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT (0U)

◆ MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_GET

#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) >> MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT)

◆ MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK

#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK (0x2U)

◆ MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SET

#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SET ( x ) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK)

◆ MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT

#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT (1U)

◆ MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_GET

#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_GET ( x ) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) >> MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT)

◆ MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK

#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK (0x1U)

◆ MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SET

#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SET ( x ) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK)

◆ MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT

#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT (0U)

◆ MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_GET

#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) >> MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT)

◆ MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK

#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK (0x1U)

◆ MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET

#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK)

◆ MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT

#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT (0U)

◆ MIPI_DSI_PCKHDL_CFG_BTA_EN_GET

#define MIPI_DSI_PCKHDL_CFG_BTA_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT)

◆ MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK

#define MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK (0x4U)

◆ MIPI_DSI_PCKHDL_CFG_BTA_EN_SET

#define MIPI_DSI_PCKHDL_CFG_BTA_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK)

◆ MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT

#define MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT (2U)

◆ MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_GET

#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT)

◆ MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK

#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK (0x10U)

◆ MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SET

#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK)

◆ MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT

#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT (4U)

◆ MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_GET

#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT)

◆ MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK

#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK (0x8U)

◆ MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SET

#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK)

◆ MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT

#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT (3U)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_GET

#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK

#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK (0x2U)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SET

#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT

#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT (1U)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_GET

#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK

#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK (0x1U)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SET

#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT

#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT (0U)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_GET

#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK

#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK (0x20U)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SET

#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK)

◆ MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT

#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT (5U)

◆ MIPI_DSI_PHY_CAL_TXSKEWCALHS_GET

#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) >> MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT)

◆ MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK

#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK (0x1U)

◆ MIPI_DSI_PHY_CAL_TXSKEWCALHS_SET

#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK)

◆ MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT

#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT (0U)

◆ MIPI_DSI_PHY_IF_CFG_N_LANES_GET

#define MIPI_DSI_PHY_IF_CFG_N_LANES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) >> MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT)

◆ MIPI_DSI_PHY_IF_CFG_N_LANES_MASK

#define MIPI_DSI_PHY_IF_CFG_N_LANES_MASK (0x3U)

◆ MIPI_DSI_PHY_IF_CFG_N_LANES_SET

#define MIPI_DSI_PHY_IF_CFG_N_LANES_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK)

◆ MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT

#define MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT (0U)

◆ MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_GET

#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) >> MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT)

◆ MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK

#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK (0xFF00U)

◆ MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET

#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK)

◆ MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT

#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT (8U)

◆ MIPI_DSI_PHY_MODE_PHY_MODE_GET

#define MIPI_DSI_PHY_MODE_PHY_MODE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) >> MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT)

◆ MIPI_DSI_PHY_MODE_PHY_MODE_MASK

#define MIPI_DSI_PHY_MODE_PHY_MODE_MASK (0x1U)

◆ MIPI_DSI_PHY_MODE_PHY_MODE_SET

#define MIPI_DSI_PHY_MODE_PHY_MODE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK)

◆ MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT

#define MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT (0U)

◆ MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_GET

#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT)

◆ MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK

#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK (0x4U)

◆ MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SET

#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK)

◆ MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT

#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT (2U)

◆ MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_GET

#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT)

◆ MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK

#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK (0x8U)

◆ MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SET

#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK)

◆ MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT

#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT (3U)

◆ MIPI_DSI_PHY_RSTZ_PHY_RSTZ_GET

#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT)

◆ MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK

#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK (0x2U)

◆ MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SET

#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK)

◆ MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT

#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT (1U)

◆ MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_GET

#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT)

◆ MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK

#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK (0x1U)

◆ MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SET

#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK)

◆ MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT

#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT (0U)

◆ MIPI_DSI_PHY_STATUS_PHY_DIRECTION_GET

#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK) >> MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK

#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK (0x2U)

◆ MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT (1U)

◆ MIPI_DSI_PHY_STATUS_PHY_LOCK_GET

#define MIPI_DSI_PHY_STATUS_PHY_LOCK_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK

#define MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK (0x1U)

◆ MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT (0U)

◆ MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK (0x40U)

◆ MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT (6U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK (0x10U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT (4U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK (0x80U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT (7U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK (0x200U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT (9U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK (0x800U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT (11U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK (0x4U)

◆ MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT (2U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK (0x20U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT (5U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK (0x100U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT (8U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK (0x400U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT (10U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_GET

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK (0x1000U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT (12U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_GET

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK (0x8U)

◆ MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT

#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT (3U)

◆ MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_GET

#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT)

◆ MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK

#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK (0x3FF0000UL)

◆ MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET

#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK)

◆ MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT

#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT (16U)

◆ MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_GET

#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT)

◆ MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK

#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK (0x3FFU)

◆ MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET

#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK)

◆ MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT

#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT (0U)

◆ MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_GET

#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT)

◆ MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK

#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK (0x3FF0000UL)

◆ MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET

#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK)

◆ MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT

#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT (16U)

◆ MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_GET

#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT)

◆ MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK

#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK (0x3FFU)

◆ MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET

#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK)

◆ MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT

#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT (0U)

◆ MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_GET

#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) >> MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT)

◆ MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK

#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK (0x7FFFU)

◆ MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SET

#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK)

◆ MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT

#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT (0U)

◆ MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_GET

#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT)

◆ MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK

#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK (0x2U)

◆ MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SET

#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK)

◆ MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT

#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT (1U)

◆ MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_GET

#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT)

◆ MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK

#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK (0x1U)

◆ MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SET

#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK)

◆ MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT

#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT (0U)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_GET

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK (0xFFU)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SET

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT (0U)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_GET

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK (0xFF00U)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT (8U)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_GET

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK (0x10000UL)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SET

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK)

◆ MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT

#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT (16U)

◆ MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_GET

#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) >> MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT)

◆ MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK

#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK (0xFU)

◆ MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SET

#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK)

◆ MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT

#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT (0U)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_GET

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK (0x2U)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SET

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT (1U)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_GET

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK (0x8U)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SET

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT (3U)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_GET

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK (0x1U)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SET

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT (0U)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_GET

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK (0x4U)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SET

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK)

◆ MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT

#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT (2U)

◆ MIPI_DSI_PWR_UP_SHUTDOWNZ_GET

#define MIPI_DSI_PWR_UP_SHUTDOWNZ_GET ( x ) (((uint32_t)(x) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) >> MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT)

◆ MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK

#define MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK (0x1U)

◆ MIPI_DSI_PWR_UP_SHUTDOWNZ_SET

#define MIPI_DSI_PWR_UP_SHUTDOWNZ_SET ( x ) (((uint32_t)(x) << MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK)

◆ MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT

#define MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT (0U)

◆ MIPI_DSI_SDF_3D_ACT_FORMAT_3D_GET

#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT)

◆ MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK

#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK (0xCU)

◆ MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT

#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT (2U)

◆ MIPI_DSI_SDF_3D_ACT_MODE_3D_GET

#define MIPI_DSI_SDF_3D_ACT_MODE_3D_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT)

◆ MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK

#define MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK (0x3U)

◆ MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT

#define MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT (0U)

◆ MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_GET

#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT)

◆ MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK

#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK (0x20U)

◆ MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT

#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT (5U)

◆ MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_GET

#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT)

◆ MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK

#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK (0x10U)

◆ MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT

#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT (4U)

◆ MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_GET

#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT)

◆ MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK

#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK (0x10000UL)

◆ MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT

#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT (16U)

◆ MIPI_DSI_SDF_3D_FORMAT_3D_GET

#define MIPI_DSI_SDF_3D_FORMAT_3D_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT)

◆ MIPI_DSI_SDF_3D_FORMAT_3D_MASK

#define MIPI_DSI_SDF_3D_FORMAT_3D_MASK (0xCU)

◆ MIPI_DSI_SDF_3D_FORMAT_3D_SET

#define MIPI_DSI_SDF_3D_FORMAT_3D_SET ( x ) (((uint32_t)(x) << MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK)

◆ MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT

#define MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT (2U)

◆ MIPI_DSI_SDF_3D_MODE_3D_GET

#define MIPI_DSI_SDF_3D_MODE_3D_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_MODE_3D_SHIFT)

◆ MIPI_DSI_SDF_3D_MODE_3D_MASK

#define MIPI_DSI_SDF_3D_MODE_3D_MASK (0x3U)

◆ MIPI_DSI_SDF_3D_MODE_3D_SET

#define MIPI_DSI_SDF_3D_MODE_3D_SET ( x ) (((uint32_t)(x) << MIPI_DSI_SDF_3D_MODE_3D_SHIFT) & MIPI_DSI_SDF_3D_MODE_3D_MASK)

◆ MIPI_DSI_SDF_3D_MODE_3D_SHIFT

#define MIPI_DSI_SDF_3D_MODE_3D_SHIFT (0U)

◆ MIPI_DSI_SDF_3D_RIGHT_FIRST_GET

#define MIPI_DSI_SDF_3D_RIGHT_FIRST_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT)

◆ MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK

#define MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK (0x20U)

◆ MIPI_DSI_SDF_3D_RIGHT_FIRST_SET

#define MIPI_DSI_SDF_3D_RIGHT_FIRST_SET ( x ) (((uint32_t)(x) << MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK)

◆ MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT

#define MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT (5U)

◆ MIPI_DSI_SDF_3D_SECOND_VSYNC_GET

#define MIPI_DSI_SDF_3D_SECOND_VSYNC_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT)

◆ MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK

#define MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK (0x10U)

◆ MIPI_DSI_SDF_3D_SECOND_VSYNC_SET

#define MIPI_DSI_SDF_3D_SECOND_VSYNC_SET ( x ) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK)

◆ MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT

#define MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT (4U)

◆ MIPI_DSI_SDF_3D_SEND_3D_CFG_GET

#define MIPI_DSI_SDF_3D_SEND_3D_CFG_GET ( x ) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT)

◆ MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK

#define MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK (0x10000UL)

◆ MIPI_DSI_SDF_3D_SEND_3D_CFG_SET

#define MIPI_DSI_SDF_3D_SEND_3D_CFG_SET ( x ) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK)

◆ MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT

#define MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT (16U)

◆ MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_GET

#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT)

◆ MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK

#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK (0xFFFF0000UL)

◆ MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET

#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET ( x ) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK)

◆ MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT

#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT (16U)

◆ MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_GET

#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_GET ( x ) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT)

◆ MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK

#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK (0xFFFFU)

◆ MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET

#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET ( x ) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK)

◆ MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT

#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT (0U)

◆ MIPI_DSI_VERSION_VERSION_GET

#define MIPI_DSI_VERSION_VERSION_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VERSION_VERSION_MASK) >> MIPI_DSI_VERSION_VERSION_SHIFT)

◆ MIPI_DSI_VERSION_VERSION_MASK

#define MIPI_DSI_VERSION_VERSION_MASK (0xFFFFFFFFUL)

◆ MIPI_DSI_VERSION_VERSION_SHIFT

#define MIPI_DSI_VERSION_VERSION_SHIFT (0U)

◆ MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_GET

#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT)

◆ MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK

#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK (0xFFFU)

◆ MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT

#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT (0U)

◆ MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_GET

#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT)

◆ MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK

#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK (0xFFFU)

◆ MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SET

#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK)

◆ MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT

#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT (0U)

◆ MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_GET

#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT)

◆ MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK

#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK (0x7FFFU)

◆ MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT

#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT (0U)

◆ MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_GET

#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT)

◆ MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK

#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK (0x7FFFU)

◆ MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SET

#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK)

◆ MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT

#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT (0U)

◆ MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_GET

#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT)

◆ MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK

#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK (0xFFFU)

◆ MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT

#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT (0U)

◆ MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_GET

#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT)

◆ MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK

#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK (0xFFFU)

◆ MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SET

#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK)

◆ MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT

#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT (0U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK (0x100U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT (8U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK (0x200U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT (9U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK (0x40U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT (6U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK (0x80U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT (7U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK (0x20U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT (5U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK (0x8U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT (3U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK (0x10U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT (4U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK (0x4U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT (2U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_GET

#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK

#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK (0x3U)

◆ MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT

#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT (0U)

◆ MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_GET

#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK (0x4000U)

◆ MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SET

#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT (14U)

◆ MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_GET

#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK (0x8000U)

◆ MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SET

#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT (15U)

◆ MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_GET

#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK (0x1000U)

◆ MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SET

#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT (12U)

◆ MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_GET

#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK (0x2000U)

◆ MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SET

#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT (13U)

◆ MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_GET

#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK (0x800U)

◆ MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SET

#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT (11U)

◆ MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_GET

#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK (0x200U)

◆ MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SET

#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT (9U)

◆ MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_GET

#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK (0x400U)

◆ MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SET

#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT (10U)

◆ MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_GET

#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK (0x100U)

◆ MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SET

#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT (8U)

◆ MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_GET

#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK

#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK (0x3U)

◆ MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET

#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK)

◆ MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT

#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT (0U)

◆ MIPI_DSI_VID_MODE_CFG_VPG_EN_GET

#define MIPI_DSI_VID_MODE_CFG_VPG_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK

#define MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK (0x10000UL)

◆ MIPI_DSI_VID_MODE_CFG_VPG_EN_SET

#define MIPI_DSI_VID_MODE_CFG_VPG_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK)

◆ MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT

#define MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT (16U)

◆ MIPI_DSI_VID_MODE_CFG_VPG_MODE_GET

#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK

#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK (0x100000UL)

◆ MIPI_DSI_VID_MODE_CFG_VPG_MODE_SET

#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK)

◆ MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT

#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT (20U)

◆ MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_GET

#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT)

◆ MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK

#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK (0x1000000UL)

◆ MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SET

#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK)

◆ MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT

#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT (24U)

◆ MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_GET

#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT)

◆ MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK

#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK (0x1FFFU)

◆ MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT

#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT (0U)

◆ MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_GET

#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT)

◆ MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK

#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK (0x1FFFU)

◆ MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SET

#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK)

◆ MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT

#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT (0U)

◆ MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_GET

#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT)

◆ MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK

#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK (0x1FFFU)

◆ MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT

#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT (0U)

◆ MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_GET

#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT)

◆ MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK

#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK (0x1FFFU)

◆ MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SET

#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK)

◆ MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT

#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT (0U)

◆ MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_GET

#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT)

◆ MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK

#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK (0x3FFFU)

◆ MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT

#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT (0U)

◆ MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_GET

#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT)

◆ MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK

#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK (0x3FFFU)

◆ MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SET

#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK)

◆ MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT

#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT (0U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_GET

#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK

#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK (0x10000UL)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT

#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT (16U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_GET

#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK

#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK (0x20000UL)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT

#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT (17U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_GET

#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK

#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK (0x1U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT

#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT (0U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_GET

#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK

#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK (0x2U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT

#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT (1U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_GET

#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK

#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK (0x4U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT

#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT (2U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_GET

#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK

#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK (0x8U)

◆ MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT

#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT (3U)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_GET

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK (0x1U)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SET

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT (0U)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_GET

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK (0x10000UL)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SET

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT (16U)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_GET

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK (0x100U)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SET

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK)

◆ MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT

#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT (8U)

◆ MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_GET

#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT)

◆ MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK

#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK (0x3FFFU)

◆ MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT

#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT (0U)

◆ MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_GET

#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT)

◆ MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK

#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK (0x3FFFU)

◆ MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SET

#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK)

◆ MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT

#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT (0U)

◆ MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_GET

#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT)

◆ MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK

#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK (0x3FFU)

◆ MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT

#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT (0U)

◆ MIPI_DSI_VID_VBP_LINES_VBP_LINES_GET

#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT)

◆ MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK

#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK (0x3FFU)

◆ MIPI_DSI_VID_VBP_LINES_VBP_LINES_SET

#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK)

◆ MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT

#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT (0U)

◆ MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_GET

#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK) >> MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT)

◆ MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK

#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK (0x3FFU)

◆ MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT

#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT (0U)

◆ MIPI_DSI_VID_VFP_LINES_VFP_LINIES_GET

#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) >> MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT)

◆ MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK

#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK (0x3FFU)

◆ MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SET

#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK)

◆ MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT

#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT (0U)

◆ MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_GET

#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT)

◆ MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK

#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK (0x3FFU)

◆ MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT

#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT (0U)

◆ MIPI_DSI_VID_VSA_LINES_VSA_LINES_GET

#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_GET ( x ) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT)

◆ MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK

#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK (0x3FFU)

◆ MIPI_DSI_VID_VSA_LINES_VSA_LINES_SET

#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SET ( x ) (((uint32_t)(x) << MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK)

◆ MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT

#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT (0U)

Data Structures

Macros