Data Structures
struct	PLA_Type

Macros
#define	PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK (0xC0000000UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT (30U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_15_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_15_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK (0x30000000UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT (28U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_14_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_14_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK (0xC000000UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT (26U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_13_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_13_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK (0x3000000UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT (24U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_12_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_12_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK (0xC00000UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT (22U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_11_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_11_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK (0x300000UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT (20U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_10_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_10_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK (0xC0000UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT (18U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_9_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_9_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK (0x30000UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT (16U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_8_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_8_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK (0xC000U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT (14U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK (0x3000U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT (12U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK (0xC00U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT (10U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK (0x300U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT (8U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK (0xC0U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT (6U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK (0x30U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT (4U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK (0xCU)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT (2U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK (0x3U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT (0U)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK (0xC0000000UL)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT (30U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK (0x30000000UL)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT (28U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK (0xC000000UL)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT (26U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK (0x3000000UL)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT (24U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK (0xC00000UL)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT (22U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK (0x300000UL)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT (20U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK (0xC0000UL)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT (18U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK (0x30000UL)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT (16U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK (0xC000U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT (14U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK (0x3000U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT (12U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK (0xC00U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT (10U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK (0x300U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT (8U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK (0xC0U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT (6U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK (0x30U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT (4U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK (0xCU)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT (2U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK (0x3U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT (0U)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK)

#define	PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK (0xC0000000UL)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT (30U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK (0x30000000UL)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT (28U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK (0xC000000UL)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT (26U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK (0x3000000UL)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT (24U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK (0xC00000UL)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT (22U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK (0x300000UL)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT (20U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK (0xC0000UL)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT (18U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK (0x30000UL)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT (16U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK (0xC000U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT (14U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK (0x3000U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT (12U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK (0xC00U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT (10U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK (0x300U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT (8U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK (0xC0U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT (6U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK (0x30U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT (4U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK (0xCU)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT (2U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK (0x3U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT (0U)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK)

#define	PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK (0xC0000000UL)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT (30U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK (0x30000000UL)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT (28U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK (0xC000000UL)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT (26U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK (0x3000000UL)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT (24U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK (0xC00000UL)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT (22U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK (0x300000UL)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT (20U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK (0xC0000UL)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT (18U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK (0x30000UL)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT (16U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK (0xC000U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT (14U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK (0x3000U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT (12U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK (0xC00U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT (10U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK (0x300U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT (8U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK (0xC0U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT (6U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK (0x30U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT (4U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK (0xCU)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT (2U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK (0x3U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT (0U)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK)

#define	PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK (0xC000U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT (14U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK (0x3000U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT (12U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK (0xC00U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT (10U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK (0x300U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT (8U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK (0xC0U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT (6U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK (0x30U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT (4U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK (0xCU)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT (2U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK (0x3U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT (0U)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK)

#define	PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT (16U)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK (0x7000U)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT (12U)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK (0x100U)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT (8U)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK)

#define	PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK (0x80U)

#define	PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT (7U)

#define	PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK)

#define	PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT)

#define	PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK (0x40U)

#define	PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT (6U)

#define	PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK)

#define	PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)

#define	PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)

#define	PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK)

#define	PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK (0x10U)

#define	PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT (4U)

#define	PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK)

#define	PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK (0x8U)

#define	PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT (3U)

#define	PLA_CHN_FILTER_2ND_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK)

#define	PLA_CHN_FILTER_2ND_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT)

#define	PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK (0x6U)

#define	PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT (1U)

#define	PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK)

#define	PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT)

#define	PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)

#define	PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)

#define	PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK)

#define	PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT (16U)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK (0x7000U)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT (12U)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK (0x100U)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT (8U)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK)

#define	PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK (0x80U)

#define	PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT (7U)

#define	PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK)

#define	PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT)

#define	PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK (0x40U)

#define	PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT (6U)

#define	PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK)

#define	PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)

#define	PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)

#define	PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK)

#define	PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK (0x10U)

#define	PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT (4U)

#define	PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK)

#define	PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK (0x8U)

#define	PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT (3U)

#define	PLA_CHN_FILTER_3RD_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK)

#define	PLA_CHN_FILTER_3RD_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT)

#define	PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK (0x6U)

#define	PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT (1U)

#define	PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK)

#define	PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT)

#define	PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)

#define	PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)

#define	PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK)

#define	PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT)

#define	PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK (0x20000UL)

#define	PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT (17U)

#define	PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK)

#define	PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) >> PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT)

#define	PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK (0x10000UL)

#define	PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT (16U)

#define	PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK)

#define	PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) >> PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT)

#define	PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK (0x10U)

#define	PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT (4U)

#define	PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK)

#define	PLA_CHN_CFG_FF_SEL_ADDER_MINUS_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) >> PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT)

#define	PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK (0x8U)

#define	PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT (3U)

#define	PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK)

#define	PLA_CHN_CFG_FF_SEL_CLK_SOURCE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) >> PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT)

#define	PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK (0x7U)

#define	PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT (0U)

#define	PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK)

#define	PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) >> PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT (16U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK (0x7000U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT (12U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK (0x100U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT (8U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK (0x80U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT (7U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK (0x40U)

#define	PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT (6U)

#define	PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)

#define	PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)

#define	PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK (0x10U)

#define	PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT (4U)

#define	PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK (0x8U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT (3U)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK)

#define	PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK (0x6U)

#define	PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT (1U)

#define	PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK)

#define	PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT)

#define	PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)

#define	PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)

#define	PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT (16U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK (0x7000U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT (12U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK (0x100U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT (8U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK (0x80U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT (7U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK (0x40U)

#define	PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT (6U)

#define	PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)

#define	PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)

#define	PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK (0x10U)

#define	PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT (4U)

#define	PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK (0x8U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT (3U)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK (0x6U)

#define	PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT (1U)

#define	PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT)

#define	PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)

#define	PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)

#define	PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK)

#define	PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK (0xFFFFU)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT (0U)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) >> PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_00 (0UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_01 (1UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_02 (2UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_03 (3UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_04 (4UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_05 (5UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_06 (6UL)

#define	PLA_CHN_AOI_16TO8_AOI_16TO8_07 (7UL)

#define	PLA_CHN_FILTER_2ND_SECOND_FILTER_0 (0UL)

#define	PLA_CHN_FILTER_2ND_SECOND_FILTER_1 (1UL)

#define	PLA_CHN_FILTER_2ND_SECOND_FILTER_2 (2UL)

#define	PLA_CHN_FILTER_2ND_SECOND_FILTER_3 (3UL)

#define	PLA_CHN_FILTER_2ND_SECOND_FILTER_4 (4UL)

#define	PLA_CHN_FILTER_2ND_SECOND_FILTER_5 (5UL)

#define	PLA_CHN_FILTER_2ND_SECOND_FILTER_6 (6UL)

#define	PLA_CHN_FILTER_2ND_SECOND_FILTER_7 (7UL)

#define	PLA_CHN_FILTER_3RD_THIRD_FILTER_0 (0UL)

#define	PLA_CHN_FILTER_3RD_THIRD_FILTER_1 (1UL)

#define	PLA_CHN_FILTER_3RD_THIRD_FILTER_2 (2UL)

#define	PLA_CHN_FILTER_3RD_THIRD_FILTER_3 (3UL)

#define	PLA_CHN_FILTER_3RD_THIRD_FILTER_4 (4UL)

#define	PLA_CHN_FILTER_3RD_THIRD_FILTER_5 (5UL)

#define	PLA_CHN_FILTER_3RD_THIRD_FILTER_6 (6UL)

#define	PLA_CHN_0 (0UL)

#define	PLA_CHN_1 (1UL)

#define	PLA_CHN_2 (2UL)

#define	PLA_CHN_3 (3UL)

#define	PLA_CHN_4 (4UL)

#define	PLA_CHN_5 (5UL)

#define	PLA_CHN_6 (6UL)

#define	PLA_CHN_7 (7UL)

#define	PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0 (0UL)

#define	PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1 (1UL)

#define	PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2 (2UL)

#define	PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3 (3UL)

#define	PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4 (4UL)

#define	PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5 (5UL)

#define	PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6 (6UL)

#define	PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7 (7UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_IN_0 (0UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0 (0UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1 (1UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2 (2UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3 (3UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4 (4UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5 (5UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6 (6UL)

#define	PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7 (7UL)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN0 (0UL)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN1 (1UL)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN2 (2UL)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN3 (3UL)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN4 (4UL)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN5 (5UL)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN6 (6UL)

#define	PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN7 (7UL)

Macro Definition Documentation

◆ PLA_CHN_0

#define PLA_CHN_0 (0UL)

◆ PLA_CHN_1

#define PLA_CHN_1 (1UL)

◆ PLA_CHN_2

#define PLA_CHN_2 (2UL)

◆ PLA_CHN_3

#define PLA_CHN_3 (3UL)

◆ PLA_CHN_4

#define PLA_CHN_4 (4UL)

◆ PLA_CHN_5

#define PLA_CHN_5 (5UL)

◆ PLA_CHN_6

#define PLA_CHN_6 (6UL)

◆ PLA_CHN_7

#define PLA_CHN_7 (7UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_00

#define PLA_CHN_AOI_16TO8_AOI_16TO8_00 (0UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_01

#define PLA_CHN_AOI_16TO8_AOI_16TO8_01 (1UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_02

#define PLA_CHN_AOI_16TO8_AOI_16TO8_02 (2UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_03

#define PLA_CHN_AOI_16TO8_AOI_16TO8_03 (3UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_04

#define PLA_CHN_AOI_16TO8_AOI_16TO8_04 (4UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_05

#define PLA_CHN_AOI_16TO8_AOI_16TO8_05 (5UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_06

#define PLA_CHN_AOI_16TO8_AOI_16TO8_06 (6UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_07

#define PLA_CHN_AOI_16TO8_AOI_16TO8_07 (7UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_0_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK (0x3U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_0_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT (0U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_10_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK (0x300000UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_10_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT (20U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_11_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK (0xC00000UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_11_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT (22U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_12_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK (0x3000000UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_12_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT (24U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_13_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK (0xC000000UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_13_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT (26U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_14_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK (0x30000000UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_14_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT (28U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_15_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK (0xC0000000UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_15_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT (30U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_1_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK (0xCU)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_1_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT (2U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_2_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK (0x30U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_2_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT (4U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_3_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK (0xC0U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_3_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT (6U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_4_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK (0x300U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_4_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT (8U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_5_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK (0xC00U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_5_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT (10U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_6_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK (0x3000U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_6_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT (12U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_7_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK (0xC000U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_7_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT (14U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_8_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK (0x30000UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_8_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT (16U)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_9_GET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK

#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK (0xC0000UL)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_9_SET

#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK)

◆ PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT

#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT (18U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK (0x3U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT (0U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK (0xCU)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT (2U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK (0x30U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT (4U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK (0xC0U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT (6U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK (0x300U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT (8U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK (0xC00U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT (10U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK (0x3000U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT (12U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK (0xC000U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT (14U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK (0x30000UL)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT (16U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK (0xC0000UL)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT (18U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK (0x300000UL)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT (20U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK (0xC00000UL)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT (22U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK (0x3000000UL)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT (24U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK (0xC000000UL)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT (26U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK (0x30000000UL)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT (28U)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_GET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK (0xC0000000UL)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SET

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK)

◆ PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT

#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT (30U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK (0x3U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT (0U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK (0xCU)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT (2U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK (0x30U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT (4U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK (0xC0U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT (6U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK (0x300U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT (8U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK (0xC00U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT (10U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK (0x3000U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT (12U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK (0xC000U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT (14U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK (0x30000UL)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT (16U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK (0xC0000UL)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT (18U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK (0x300000UL)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT (20U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK (0xC00000UL)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT (22U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK (0x3000000UL)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT (24U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK (0xC000000UL)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT (26U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK (0x30000000UL)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT (28U)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_GET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK (0xC0000000UL)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SET

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK)

◆ PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT

#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT (30U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK (0x3U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT (0U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK (0xCU)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT (2U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK (0x30U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT (4U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK (0xC0U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT (6U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK (0x300U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT (8U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK (0xC00U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT (10U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK (0x3000U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT (12U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK (0xC000U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT (14U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK (0x30000UL)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT (16U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK (0xC0000UL)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT (18U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK (0x300000UL)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT (20U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK (0xC00000UL)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT (22U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK (0x3000000UL)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT (24U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK (0xC000000UL)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT (26U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK (0x30000000UL)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT (28U)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_GET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK (0xC0000000UL)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SET

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK)

◆ PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT

#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT (30U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_GET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK (0x3U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT (0U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_GET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK (0xCU)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT (2U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_GET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK (0x30U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT (4U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_GET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK (0xC0U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT (6U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_GET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK (0x300U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT (8U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_GET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK (0xC00U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT (10U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_GET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK (0x3000U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT (12U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_GET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_GET ( x ) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK (0xC000U)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SET

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SET ( x ) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK)

◆ PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT

#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT (14U)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN0

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN0 (0UL)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN1

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN1 (1UL)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN2

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN2 (2UL)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN3

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN3 (3UL)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN4

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN4 (4UL)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN5

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN5 (5UL)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN6

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN6 (6UL)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN7

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN7 (7UL)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_GET

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_GET ( x ) (((uint32_t)(x) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) >> PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK (0xFFFFU)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SET

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SET ( x ) (((uint32_t)(x) << PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK)

◆ PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT

#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT (0U)

◆ PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_GET

#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_GET ( x ) (((uint32_t)(x) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) >> PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT)

◆ PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK

#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK (0x10000UL)

◆ PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SET

#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SET ( x ) (((uint32_t)(x) << PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK)

◆ PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT

#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT (16U)

◆ PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_GET

#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_GET ( x ) (((uint32_t)(x) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) >> PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT)

◆ PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK

#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK (0x20000UL)

◆ PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SET

#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SET ( x ) (((uint32_t)(x) << PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK)

◆ PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT

#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT (17U)

◆ PLA_CHN_CFG_FF_SEL_ADDER_MINUS_GET

#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_GET ( x ) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) >> PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT)

◆ PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK

#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK (0x10U)

◆ PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SET

#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SET ( x ) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK)

◆ PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT

#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT (4U)

◆ PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_GET

#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_GET ( x ) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) >> PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT)

◆ PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK

#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK (0x7U)

◆ PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SET

#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SET ( x ) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK)

◆ PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT

#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT (0U)

◆ PLA_CHN_CFG_FF_SEL_CLK_SOURCE_GET

#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_GET ( x ) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) >> PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT)

◆ PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK

#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK (0x8U)

◆ PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SET

#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SET ( x ) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK)

◆ PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT

#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT (3U)

◆ PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_GET

#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK

#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK (0x10U)

◆ PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SET

#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK)

◆ PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT

#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT (4U)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_GET

#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK

#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SET

#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT

#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT (16U)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_GET

#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK

#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK (0x100U)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SET

#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT

#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT (8U)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_GET

#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK

#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK (0x7000U)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SET

#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK)

◆ PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT

#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT (12U)

◆ PLA_CHN_FILTER_2ND_FILTER_REVERSE_GET

#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT)

◆ PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK

#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK (0x8U)

◆ PLA_CHN_FILTER_2ND_FILTER_REVERSE_SET

#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK)

◆ PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT

#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT (3U)

◆ PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_GET

#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT)

◆ PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK

#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK (0x80U)

◆ PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SET

#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK)

◆ PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT

#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT (7U)

◆ PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_GET

#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK

#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)

◆ PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SET

#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK)

◆ PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT

#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)

◆ PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_GET

#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK

#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK (0x40U)

◆ PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SET

#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK)

◆ PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT

#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT (6U)

◆ PLA_CHN_FILTER_2ND_SECOND_FILTER_0

#define PLA_CHN_FILTER_2ND_SECOND_FILTER_0 (0UL)

◆ PLA_CHN_FILTER_2ND_SECOND_FILTER_1

#define PLA_CHN_FILTER_2ND_SECOND_FILTER_1 (1UL)

◆ PLA_CHN_FILTER_2ND_SECOND_FILTER_2

#define PLA_CHN_FILTER_2ND_SECOND_FILTER_2 (2UL)

◆ PLA_CHN_FILTER_2ND_SECOND_FILTER_3

#define PLA_CHN_FILTER_2ND_SECOND_FILTER_3 (3UL)

◆ PLA_CHN_FILTER_2ND_SECOND_FILTER_4

#define PLA_CHN_FILTER_2ND_SECOND_FILTER_4 (4UL)

◆ PLA_CHN_FILTER_2ND_SECOND_FILTER_5

#define PLA_CHN_FILTER_2ND_SECOND_FILTER_5 (5UL)

◆ PLA_CHN_FILTER_2ND_SECOND_FILTER_6

#define PLA_CHN_FILTER_2ND_SECOND_FILTER_6 (6UL)

◆ PLA_CHN_FILTER_2ND_SECOND_FILTER_7

#define PLA_CHN_FILTER_2ND_SECOND_FILTER_7 (7UL)

◆ PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_GET

#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT)

◆ PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK

#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK (0x6U)

◆ PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SET

#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK)

◆ PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT

#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT (1U)

◆ PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_GET

#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK

#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)

◆ PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SET

#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK)

◆ PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT

#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)

◆ PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_GET

#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK

#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK (0x10U)

◆ PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SET

#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK)

◆ PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT

#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT (4U)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_GET

#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK

#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SET

#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT

#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT (16U)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_GET

#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK

#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK (0x100U)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SET

#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT

#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT (8U)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_GET

#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK

#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK (0x7000U)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SET

#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK)

◆ PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT

#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT (12U)

◆ PLA_CHN_FILTER_3RD_FILTER_REVERSE_GET

#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT)

◆ PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK

#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK (0x8U)

◆ PLA_CHN_FILTER_3RD_FILTER_REVERSE_SET

#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK)

◆ PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT

#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT (3U)

◆ PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_GET

#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT)

◆ PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK

#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK (0x80U)

◆ PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SET

#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK)

◆ PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT

#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT (7U)

◆ PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_GET

#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK

#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)

◆ PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SET

#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK)

◆ PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT

#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)

◆ PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_GET

#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK

#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK (0x40U)

◆ PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SET

#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK)

◆ PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT

#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT (6U)

◆ PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_GET

#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT)

◆ PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK

#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK (0x6U)

◆ PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SET

#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK)

◆ PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT

#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT (1U)

◆ PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_GET

#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT)

◆ PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK

#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)

◆ PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SET

#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK)

◆ PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT

#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)

◆ PLA_CHN_FILTER_3RD_THIRD_FILTER_0

#define PLA_CHN_FILTER_3RD_THIRD_FILTER_0 (0UL)

◆ PLA_CHN_FILTER_3RD_THIRD_FILTER_1

#define PLA_CHN_FILTER_3RD_THIRD_FILTER_1 (1UL)

◆ PLA_CHN_FILTER_3RD_THIRD_FILTER_2

#define PLA_CHN_FILTER_3RD_THIRD_FILTER_2 (2UL)

◆ PLA_CHN_FILTER_3RD_THIRD_FILTER_3

#define PLA_CHN_FILTER_3RD_THIRD_FILTER_3 (3UL)

◆ PLA_CHN_FILTER_3RD_THIRD_FILTER_4

#define PLA_CHN_FILTER_3RD_THIRD_FILTER_4 (4UL)

◆ PLA_CHN_FILTER_3RD_THIRD_FILTER_5

#define PLA_CHN_FILTER_3RD_THIRD_FILTER_5 (5UL)

◆ PLA_CHN_FILTER_3RD_THIRD_FILTER_6

#define PLA_CHN_FILTER_3RD_THIRD_FILTER_6 (6UL)

◆ PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_GET

#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK (0x10U)

◆ PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SET

#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT (4U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_GET

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SET

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT (16U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_GET

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK (0x100U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SET

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT (8U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_GET

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK (0x7000U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SET

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT

#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT (12U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_GET

#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK

#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK (0x8U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SET

#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT

#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT (3U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_GET

#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK

#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK (0x80U)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SET

#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK)

◆ PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT

#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT (7U)

◆ PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0

#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0 (0UL)

◆ PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1

#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1 (1UL)

◆ PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2

#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2 (2UL)

◆ PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3

#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3 (3UL)

◆ PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4

#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4 (4UL)

◆ PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5

#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5 (5UL)

◆ PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6

#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6 (6UL)

◆ PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7

#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7 (7UL)

◆ PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_GET

#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)

◆ PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SET

#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)

◆ PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_GET

#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK (0x40U)

◆ PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SET

#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT (6U)

◆ PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_GET

#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK

#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK (0x6U)

◆ PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SET

#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK)

◆ PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT

#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT (1U)

◆ PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_GET

#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)

◆ PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SET

#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)

◆ PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_GET

#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK (0x10U)

◆ PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SET

#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT (4U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_GET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT (16U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_GET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK (0x100U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT (8U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_GET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK (0x7000U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT (12U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_GET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK

#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK (0x8U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT (3U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_GET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK

#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK (0x80U)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SET

#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT (7U)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_IN_0

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_IN_0 (0UL)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0 (0UL)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1 (1UL)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2 (2UL)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3 (3UL)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4 (4UL)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5 (5UL)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6 (6UL)

◆ PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7

#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7 (7UL)

◆ PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_GET

#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK (0x20U)

◆ PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SET

#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT (5U)

◆ PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_GET

#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK (0x40U)

◆ PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SET

#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT (6U)

◆ PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_GET

#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK

#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK (0x6U)

◆ PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SET

#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT (1U)

◆ PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_GET

#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_GET ( x ) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT)

◆ PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK

#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U)

◆ PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SET

#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SET ( x ) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK)

◆ PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT

#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U)

Data Structures

Macros