hpm_pllctl_regs.h File Reference

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Data Structures
struct	PLLCTL_Type

Macros
#define	PLLCTL_XTAL_RESPONSE_MASK   (0x20000000UL)
#define	PLLCTL_XTAL_RESPONSE_SHIFT   (29U)
#define	PLLCTL_XTAL_RESPONSE_GET(x)   (((uint32_t)(x) & PLLCTL_XTAL_RESPONSE_MASK) >> PLLCTL_XTAL_RESPONSE_SHIFT)
#define	PLLCTL_XTAL_ENABLE_MASK   (0x10000000UL)
#define	PLLCTL_XTAL_ENABLE_SHIFT   (28U)
#define	PLLCTL_XTAL_ENABLE_GET(x)   (((uint32_t)(x) & PLLCTL_XTAL_ENABLE_MASK) >> PLLCTL_XTAL_ENABLE_SHIFT)
#define	PLLCTL_XTAL_RAMP_TIME_MASK   (0xFFFFFUL)
#define	PLLCTL_XTAL_RAMP_TIME_SHIFT   (0U)
#define	PLLCTL_XTAL_RAMP_TIME_SET(x)   (((uint32_t)(x) << PLLCTL_XTAL_RAMP_TIME_SHIFT) & PLLCTL_XTAL_RAMP_TIME_MASK)
#define	PLLCTL_XTAL_RAMP_TIME_GET(x)   (((uint32_t)(x) & PLLCTL_XTAL_RAMP_TIME_MASK) >> PLLCTL_XTAL_RAMP_TIME_SHIFT)
#define	PLLCTL_PLL_CFG0_SS_RSTPTR_MASK   (0x80000000UL)
#define	PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT   (31U)
#define	PLLCTL_PLL_CFG0_SS_RSTPTR_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK)
#define	PLLCTL_PLL_CFG0_SS_RSTPTR_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK) >> PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT)
#define	PLLCTL_PLL_CFG0_REFDIV_MASK   (0x3F000000UL)
#define	PLLCTL_PLL_CFG0_REFDIV_SHIFT   (24U)
#define	PLLCTL_PLL_CFG0_REFDIV_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_REFDIV_SHIFT) & PLLCTL_PLL_CFG0_REFDIV_MASK)
#define	PLLCTL_PLL_CFG0_REFDIV_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_REFDIV_MASK) >> PLLCTL_PLL_CFG0_REFDIV_SHIFT)
#define	PLLCTL_PLL_CFG0_POSTDIV1_MASK   (0x700000UL)
#define	PLLCTL_PLL_CFG0_POSTDIV1_SHIFT   (20U)
#define	PLLCTL_PLL_CFG0_POSTDIV1_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) & PLLCTL_PLL_CFG0_POSTDIV1_MASK)
#define	PLLCTL_PLL_CFG0_POSTDIV1_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_POSTDIV1_MASK) >> PLLCTL_PLL_CFG0_POSTDIV1_SHIFT)
#define	PLLCTL_PLL_CFG0_SS_SPREAD_MASK   (0x7C000UL)
#define	PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT   (14U)
#define	PLLCTL_PLL_CFG0_SS_SPREAD_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK)
#define	PLLCTL_PLL_CFG0_SS_SPREAD_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT)
#define	PLLCTL_PLL_CFG0_SS_DIVVAL_MASK   (0x3F00U)
#define	PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT   (8U)
#define	PLLCTL_PLL_CFG0_SS_DIVVAL_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK)
#define	PLLCTL_PLL_CFG0_SS_DIVVAL_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT)
#define	PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK   (0x80U)
#define	PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT   (7U)
#define	PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK)
#define	PLLCTL_PLL_CFG0_SS_DOWNSPREAD_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT)
#define	PLLCTL_PLL_CFG0_SS_RESET_MASK   (0x40U)
#define	PLLCTL_PLL_CFG0_SS_RESET_SHIFT   (6U)
#define	PLLCTL_PLL_CFG0_SS_RESET_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RESET_SHIFT) & PLLCTL_PLL_CFG0_SS_RESET_MASK)
#define	PLLCTL_PLL_CFG0_SS_RESET_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RESET_MASK) >> PLLCTL_PLL_CFG0_SS_RESET_SHIFT)
#define	PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK   (0x20U)
#define	PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT   (5U)
#define	PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK)
#define	PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) >> PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT)
#define	PLLCTL_PLL_CFG0_DSMPD_MASK   (0x8U)
#define	PLLCTL_PLL_CFG0_DSMPD_SHIFT   (3U)
#define	PLLCTL_PLL_CFG0_DSMPD_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG0_DSMPD_SHIFT) & PLLCTL_PLL_CFG0_DSMPD_MASK)
#define	PLLCTL_PLL_CFG0_DSMPD_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG0_DSMPD_MASK) >> PLLCTL_PLL_CFG0_DSMPD_SHIFT)
#define	PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK   (0x80000000UL)
#define	PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT   (31U)
#define	PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK)
#define	PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) >> PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT)
#define	PLLCTL_PLL_CFG1_CLKEN_SW_MASK   (0x4000000UL)
#define	PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT   (26U)
#define	PLLCTL_PLL_CFG1_CLKEN_SW_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK)
#define	PLLCTL_PLL_CFG1_CLKEN_SW_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK) >> PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT)
#define	PLLCTL_PLL_CFG1_PLLPD_SW_MASK   (0x2000000UL)
#define	PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT   (25U)
#define	PLLCTL_PLL_CFG1_PLLPD_SW_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK)
#define	PLLCTL_PLL_CFG1_PLLPD_SW_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) >> PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT)
#define	PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK   (0x8000U)
#define	PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT   (15U)
#define	PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK)
#define	PLLCTL_PLL_CFG1_LOCK_CNT_CFG_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK) >> PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT)
#define	PLLCTL_PLL_CFG2_FBDIV_INT_MASK   (0xFFFU)
#define	PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT   (0U)
#define	PLLCTL_PLL_CFG2_FBDIV_INT_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK)
#define	PLLCTL_PLL_CFG2_FBDIV_INT_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK) >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT)
#define	PLLCTL_PLL_FREQ_FRAC_MASK   (0xFFFFFF00UL)
#define	PLLCTL_PLL_FREQ_FRAC_SHIFT   (8U)
#define	PLLCTL_PLL_FREQ_FRAC_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_FREQ_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FRAC_MASK)
#define	PLLCTL_PLL_FREQ_FRAC_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_FREQ_FRAC_MASK) >> PLLCTL_PLL_FREQ_FRAC_SHIFT)
#define	PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK   (0xFFU)
#define	PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT   (0U)
#define	PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK)
#define	PLLCTL_PLL_FREQ_FBDIV_FRAC_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK) >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT)
#define	PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK   (0x80000000UL)
#define	PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT   (31U)
#define	PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK)
#define	PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT)
#define	PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK   (0x1000000UL)
#define	PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT   (24U)
#define	PLLCTL_PLL_LOCK_LOCK_REFDIV_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK)
#define	PLLCTL_PLL_LOCK_LOCK_REFDIV_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK) >> PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT)
#define	PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK   (0x100000UL)
#define	PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT   (20U)
#define	PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK)
#define	PLLCTL_PLL_LOCK_LOCK_POSTDIV1_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK) >> PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT)
#define	PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK   (0x4000U)
#define	PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT   (14U)
#define	PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK)
#define	PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT)
#define	PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK   (0x100U)
#define	PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT   (8U)
#define	PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK)
#define	PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT)
#define	PLLCTL_PLL_STATUS_ENABLE_MASK   (0x8000000UL)
#define	PLLCTL_PLL_STATUS_ENABLE_SHIFT   (27U)
#define	PLLCTL_PLL_STATUS_ENABLE_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_STATUS_ENABLE_MASK) >> PLLCTL_PLL_STATUS_ENABLE_SHIFT)
#define	PLLCTL_PLL_STATUS_RESPONSE_MASK   (0x4U)
#define	PLLCTL_PLL_STATUS_RESPONSE_SHIFT   (2U)
#define	PLLCTL_PLL_STATUS_RESPONSE_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_STATUS_RESPONSE_MASK) >> PLLCTL_PLL_STATUS_RESPONSE_SHIFT)
#define	PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK   (0x2U)
#define	PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT   (1U)
#define	PLLCTL_PLL_STATUS_PLL_LOCK_COMB_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT)
#define	PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK   (0x1U)
#define	PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT   (0U)
#define	PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT)
#define	PLLCTL_PLL_DIV0_BUSY_MASK   (0x80000000UL)
#define	PLLCTL_PLL_DIV0_BUSY_SHIFT   (31U)
#define	PLLCTL_PLL_DIV0_BUSY_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_DIV0_BUSY_MASK) >> PLLCTL_PLL_DIV0_BUSY_SHIFT)
#define	PLLCTL_PLL_DIV0_RESPONSE_MASK   (0x20000000UL)
#define	PLLCTL_PLL_DIV0_RESPONSE_SHIFT   (29U)
#define	PLLCTL_PLL_DIV0_RESPONSE_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_DIV0_RESPONSE_MASK) >> PLLCTL_PLL_DIV0_RESPONSE_SHIFT)
#define	PLLCTL_PLL_DIV0_ENABLE_MASK   (0x10000000UL)
#define	PLLCTL_PLL_DIV0_ENABLE_SHIFT   (28U)
#define	PLLCTL_PLL_DIV0_ENABLE_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_DIV0_ENABLE_MASK) >> PLLCTL_PLL_DIV0_ENABLE_SHIFT)
#define	PLLCTL_PLL_DIV0_DIV_MASK   (0xFFU)
#define	PLLCTL_PLL_DIV0_DIV_SHIFT   (0U)
#define	PLLCTL_PLL_DIV0_DIV_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_DIV0_DIV_SHIFT) & PLLCTL_PLL_DIV0_DIV_MASK)
#define	PLLCTL_PLL_DIV0_DIV_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_DIV0_DIV_MASK) >> PLLCTL_PLL_DIV0_DIV_SHIFT)
#define	PLLCTL_PLL_DIV1_BUSY_MASK   (0x80000000UL)
#define	PLLCTL_PLL_DIV1_BUSY_SHIFT   (31U)
#define	PLLCTL_PLL_DIV1_BUSY_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_DIV1_BUSY_MASK) >> PLLCTL_PLL_DIV1_BUSY_SHIFT)
#define	PLLCTL_PLL_DIV1_RESPONSE_MASK   (0x20000000UL)
#define	PLLCTL_PLL_DIV1_RESPONSE_SHIFT   (29U)
#define	PLLCTL_PLL_DIV1_RESPONSE_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_DIV1_RESPONSE_MASK) >> PLLCTL_PLL_DIV1_RESPONSE_SHIFT)
#define	PLLCTL_PLL_DIV1_ENABLE_MASK   (0x10000000UL)
#define	PLLCTL_PLL_DIV1_ENABLE_SHIFT   (28U)
#define	PLLCTL_PLL_DIV1_ENABLE_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_DIV1_ENABLE_MASK) >> PLLCTL_PLL_DIV1_ENABLE_SHIFT)
#define	PLLCTL_PLL_DIV1_DIV_MASK   (0xFFU)
#define	PLLCTL_PLL_DIV1_DIV_SHIFT   (0U)
#define	PLLCTL_PLL_DIV1_DIV_SET(x)   (((uint32_t)(x) << PLLCTL_PLL_DIV1_DIV_SHIFT) & PLLCTL_PLL_DIV1_DIV_MASK)
#define	PLLCTL_PLL_DIV1_DIV_GET(x)   (((uint32_t)(x) & PLLCTL_PLL_DIV1_DIV_MASK) >> PLLCTL_PLL_DIV1_DIV_SHIFT)
#define	PLLCTL_PLL_PLL0   (0UL)
#define	PLLCTL_PLL_PLL1   (1UL)
#define	PLLCTL_PLL_PLL2   (2UL)
#define	PLLCTL_PLL_PLL3   (3UL)
#define	PLLCTL_PLL_PLL4   (4UL)

Macro Definition Documentation

PLLCTL_PLL_CFG0_DSMPD_GET

#define PLLCTL_PLL_CFG0_DSMPD_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_DSMPD_MASK) >> PLLCTL_PLL_CFG0_DSMPD_SHIFT)

PLLCTL_PLL_CFG0_DSMPD_MASK

#define PLLCTL_PLL_CFG0_DSMPD_MASK   (0x8U)

PLLCTL_PLL_CFG0_DSMPD_SET

#define PLLCTL_PLL_CFG0_DSMPD_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_DSMPD_SHIFT) & PLLCTL_PLL_CFG0_DSMPD_MASK)

PLLCTL_PLL_CFG0_DSMPD_SHIFT

#define PLLCTL_PLL_CFG0_DSMPD_SHIFT   (3U)

PLLCTL_PLL_CFG0_POSTDIV1_GET

#define PLLCTL_PLL_CFG0_POSTDIV1_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_POSTDIV1_MASK) >> PLLCTL_PLL_CFG0_POSTDIV1_SHIFT)

PLLCTL_PLL_CFG0_POSTDIV1_MASK

#define PLLCTL_PLL_CFG0_POSTDIV1_MASK   (0x700000UL)

PLLCTL_PLL_CFG0_POSTDIV1_SET

#define PLLCTL_PLL_CFG0_POSTDIV1_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) & PLLCTL_PLL_CFG0_POSTDIV1_MASK)

PLLCTL_PLL_CFG0_POSTDIV1_SHIFT

#define PLLCTL_PLL_CFG0_POSTDIV1_SHIFT   (20U)

PLLCTL_PLL_CFG0_REFDIV_GET

#define PLLCTL_PLL_CFG0_REFDIV_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_REFDIV_MASK) >> PLLCTL_PLL_CFG0_REFDIV_SHIFT)

PLLCTL_PLL_CFG0_REFDIV_MASK

#define PLLCTL_PLL_CFG0_REFDIV_MASK   (0x3F000000UL)

PLLCTL_PLL_CFG0_REFDIV_SET

#define PLLCTL_PLL_CFG0_REFDIV_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_REFDIV_SHIFT) & PLLCTL_PLL_CFG0_REFDIV_MASK)

PLLCTL_PLL_CFG0_REFDIV_SHIFT

#define PLLCTL_PLL_CFG0_REFDIV_SHIFT   (24U)

PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_GET

#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) >> PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT)

PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK

#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK   (0x20U)

PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SET

#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK)

PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT

#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT   (5U)

PLLCTL_PLL_CFG0_SS_DIVVAL_GET

#define PLLCTL_PLL_CFG0_SS_DIVVAL_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT)

PLLCTL_PLL_CFG0_SS_DIVVAL_MASK

#define PLLCTL_PLL_CFG0_SS_DIVVAL_MASK   (0x3F00U)

PLLCTL_PLL_CFG0_SS_DIVVAL_SET

#define PLLCTL_PLL_CFG0_SS_DIVVAL_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK)

PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT

#define PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT   (8U)

PLLCTL_PLL_CFG0_SS_DOWNSPREAD_GET

#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT)

PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK

#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK   (0x80U)

PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SET

#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK)

PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT

#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT   (7U)

PLLCTL_PLL_CFG0_SS_RESET_GET

#define PLLCTL_PLL_CFG0_SS_RESET_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RESET_MASK) >> PLLCTL_PLL_CFG0_SS_RESET_SHIFT)

PLLCTL_PLL_CFG0_SS_RESET_MASK

#define PLLCTL_PLL_CFG0_SS_RESET_MASK   (0x40U)

PLLCTL_PLL_CFG0_SS_RESET_SET

#define PLLCTL_PLL_CFG0_SS_RESET_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RESET_SHIFT) & PLLCTL_PLL_CFG0_SS_RESET_MASK)

PLLCTL_PLL_CFG0_SS_RESET_SHIFT

#define PLLCTL_PLL_CFG0_SS_RESET_SHIFT   (6U)

PLLCTL_PLL_CFG0_SS_RSTPTR_GET

#define PLLCTL_PLL_CFG0_SS_RSTPTR_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK) >> PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT)

PLLCTL_PLL_CFG0_SS_RSTPTR_MASK

#define PLLCTL_PLL_CFG0_SS_RSTPTR_MASK   (0x80000000UL)

PLLCTL_PLL_CFG0_SS_RSTPTR_SET

#define PLLCTL_PLL_CFG0_SS_RSTPTR_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK)

PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT

#define PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT   (31U)

PLLCTL_PLL_CFG0_SS_SPREAD_GET

#define PLLCTL_PLL_CFG0_SS_SPREAD_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT)

PLLCTL_PLL_CFG0_SS_SPREAD_MASK

#define PLLCTL_PLL_CFG0_SS_SPREAD_MASK   (0x7C000UL)

PLLCTL_PLL_CFG0_SS_SPREAD_SET

#define PLLCTL_PLL_CFG0_SS_SPREAD_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK)

PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT

#define PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT   (14U)

PLLCTL_PLL_CFG1_CLKEN_SW_GET

#define PLLCTL_PLL_CFG1_CLKEN_SW_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK) >> PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT)

PLLCTL_PLL_CFG1_CLKEN_SW_MASK

#define PLLCTL_PLL_CFG1_CLKEN_SW_MASK   (0x4000000UL)

PLLCTL_PLL_CFG1_CLKEN_SW_SET

#define PLLCTL_PLL_CFG1_CLKEN_SW_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK)

PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT

#define PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT   (26U)

PLLCTL_PLL_CFG1_LOCK_CNT_CFG_GET

#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK) >> PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT)

PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK

#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK   (0x8000U)

PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SET

#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK)

PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT

#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT   (15U)

PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_GET

#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) >> PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT)

PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK

#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK   (0x80000000UL)

PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SET

#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK)

PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT

#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT   (31U)

PLLCTL_PLL_CFG1_PLLPD_SW_GET

#define PLLCTL_PLL_CFG1_PLLPD_SW_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) >> PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT)

PLLCTL_PLL_CFG1_PLLPD_SW_MASK

#define PLLCTL_PLL_CFG1_PLLPD_SW_MASK   (0x2000000UL)

PLLCTL_PLL_CFG1_PLLPD_SW_SET

#define PLLCTL_PLL_CFG1_PLLPD_SW_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK)

PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT

#define PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT   (25U)

PLLCTL_PLL_CFG2_FBDIV_INT_GET

#define PLLCTL_PLL_CFG2_FBDIV_INT_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK) >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT)

PLLCTL_PLL_CFG2_FBDIV_INT_MASK

#define PLLCTL_PLL_CFG2_FBDIV_INT_MASK   (0xFFFU)

PLLCTL_PLL_CFG2_FBDIV_INT_SET

#define PLLCTL_PLL_CFG2_FBDIV_INT_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK)

PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT

#define PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT   (0U)

PLLCTL_PLL_DIV0_BUSY_GET

#define PLLCTL_PLL_DIV0_BUSY_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_DIV0_BUSY_MASK) >> PLLCTL_PLL_DIV0_BUSY_SHIFT)

PLLCTL_PLL_DIV0_BUSY_MASK

#define PLLCTL_PLL_DIV0_BUSY_MASK   (0x80000000UL)

PLLCTL_PLL_DIV0_BUSY_SHIFT

#define PLLCTL_PLL_DIV0_BUSY_SHIFT   (31U)

PLLCTL_PLL_DIV0_DIV_GET

#define PLLCTL_PLL_DIV0_DIV_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_DIV0_DIV_MASK) >> PLLCTL_PLL_DIV0_DIV_SHIFT)

PLLCTL_PLL_DIV0_DIV_MASK

#define PLLCTL_PLL_DIV0_DIV_MASK   (0xFFU)

PLLCTL_PLL_DIV0_DIV_SET

#define PLLCTL_PLL_DIV0_DIV_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_DIV0_DIV_SHIFT) & PLLCTL_PLL_DIV0_DIV_MASK)

PLLCTL_PLL_DIV0_DIV_SHIFT

#define PLLCTL_PLL_DIV0_DIV_SHIFT   (0U)

PLLCTL_PLL_DIV0_ENABLE_GET

#define PLLCTL_PLL_DIV0_ENABLE_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_DIV0_ENABLE_MASK) >> PLLCTL_PLL_DIV0_ENABLE_SHIFT)

PLLCTL_PLL_DIV0_ENABLE_MASK

#define PLLCTL_PLL_DIV0_ENABLE_MASK   (0x10000000UL)

PLLCTL_PLL_DIV0_ENABLE_SHIFT

#define PLLCTL_PLL_DIV0_ENABLE_SHIFT   (28U)

PLLCTL_PLL_DIV0_RESPONSE_GET

#define PLLCTL_PLL_DIV0_RESPONSE_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_DIV0_RESPONSE_MASK) >> PLLCTL_PLL_DIV0_RESPONSE_SHIFT)

PLLCTL_PLL_DIV0_RESPONSE_MASK

#define PLLCTL_PLL_DIV0_RESPONSE_MASK   (0x20000000UL)

PLLCTL_PLL_DIV0_RESPONSE_SHIFT

#define PLLCTL_PLL_DIV0_RESPONSE_SHIFT   (29U)

PLLCTL_PLL_DIV1_BUSY_GET

#define PLLCTL_PLL_DIV1_BUSY_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_DIV1_BUSY_MASK) >> PLLCTL_PLL_DIV1_BUSY_SHIFT)

PLLCTL_PLL_DIV1_BUSY_MASK

#define PLLCTL_PLL_DIV1_BUSY_MASK   (0x80000000UL)

PLLCTL_PLL_DIV1_BUSY_SHIFT

#define PLLCTL_PLL_DIV1_BUSY_SHIFT   (31U)

PLLCTL_PLL_DIV1_DIV_GET

#define PLLCTL_PLL_DIV1_DIV_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_DIV1_DIV_MASK) >> PLLCTL_PLL_DIV1_DIV_SHIFT)

PLLCTL_PLL_DIV1_DIV_MASK

#define PLLCTL_PLL_DIV1_DIV_MASK   (0xFFU)

PLLCTL_PLL_DIV1_DIV_SET

#define PLLCTL_PLL_DIV1_DIV_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_DIV1_DIV_SHIFT) & PLLCTL_PLL_DIV1_DIV_MASK)

PLLCTL_PLL_DIV1_DIV_SHIFT

#define PLLCTL_PLL_DIV1_DIV_SHIFT   (0U)

PLLCTL_PLL_DIV1_ENABLE_GET

#define PLLCTL_PLL_DIV1_ENABLE_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_DIV1_ENABLE_MASK) >> PLLCTL_PLL_DIV1_ENABLE_SHIFT)

PLLCTL_PLL_DIV1_ENABLE_MASK

#define PLLCTL_PLL_DIV1_ENABLE_MASK   (0x10000000UL)

PLLCTL_PLL_DIV1_ENABLE_SHIFT

#define PLLCTL_PLL_DIV1_ENABLE_SHIFT   (28U)

PLLCTL_PLL_DIV1_RESPONSE_GET

#define PLLCTL_PLL_DIV1_RESPONSE_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_DIV1_RESPONSE_MASK) >> PLLCTL_PLL_DIV1_RESPONSE_SHIFT)

PLLCTL_PLL_DIV1_RESPONSE_MASK

#define PLLCTL_PLL_DIV1_RESPONSE_MASK   (0x20000000UL)

PLLCTL_PLL_DIV1_RESPONSE_SHIFT

#define PLLCTL_PLL_DIV1_RESPONSE_SHIFT   (29U)

PLLCTL_PLL_FREQ_FBDIV_FRAC_GET

#define PLLCTL_PLL_FREQ_FBDIV_FRAC_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK) >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT)

PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK

#define PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK   (0xFFU)

PLLCTL_PLL_FREQ_FBDIV_FRAC_SET

#define PLLCTL_PLL_FREQ_FBDIV_FRAC_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK)

PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT

#define PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT   (0U)

PLLCTL_PLL_FREQ_FRAC_GET

#define PLLCTL_PLL_FREQ_FRAC_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_FREQ_FRAC_MASK) >> PLLCTL_PLL_FREQ_FRAC_SHIFT)

PLLCTL_PLL_FREQ_FRAC_MASK

#define PLLCTL_PLL_FREQ_FRAC_MASK   (0xFFFFFF00UL)

PLLCTL_PLL_FREQ_FRAC_SET

#define PLLCTL_PLL_FREQ_FRAC_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_FREQ_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FRAC_MASK)

PLLCTL_PLL_FREQ_FRAC_SHIFT

#define PLLCTL_PLL_FREQ_FRAC_SHIFT   (8U)

PLLCTL_PLL_LOCK_LOCK_POSTDIV1_GET

#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK) >> PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT)

PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK

#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK   (0x100000UL)

PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SET

#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK)

PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT

#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT   (20U)

PLLCTL_PLL_LOCK_LOCK_REFDIV_GET

#define PLLCTL_PLL_LOCK_LOCK_REFDIV_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK) >> PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT)

PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK

#define PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK   (0x1000000UL)

PLLCTL_PLL_LOCK_LOCK_REFDIV_SET

#define PLLCTL_PLL_LOCK_LOCK_REFDIV_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK)

PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT

#define PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT   (24U)

PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_GET

#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT)

PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK

#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK   (0x100U)

PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SET

#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK)

PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT

#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT   (8U)

PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_GET

#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT)

PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK

#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK   (0x80000000UL)

PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SET

#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK)

PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT

#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT   (31U)

PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_GET

#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT)

PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK

#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK   (0x4000U)

PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SET

#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SET

(

x

)

(((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK)

PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT

#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT   (14U)

PLLCTL_PLL_PLL0

#define PLLCTL_PLL_PLL0   (0UL)

PLLCTL_PLL_PLL1

#define PLLCTL_PLL_PLL1   (1UL)

PLLCTL_PLL_PLL2

#define PLLCTL_PLL_PLL2   (2UL)

PLLCTL_PLL_PLL3

#define PLLCTL_PLL_PLL3   (3UL)

PLLCTL_PLL_PLL4

#define PLLCTL_PLL_PLL4   (4UL)

PLLCTL_PLL_STATUS_ENABLE_GET

#define PLLCTL_PLL_STATUS_ENABLE_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_STATUS_ENABLE_MASK) >> PLLCTL_PLL_STATUS_ENABLE_SHIFT)

PLLCTL_PLL_STATUS_ENABLE_MASK

#define PLLCTL_PLL_STATUS_ENABLE_MASK   (0x8000000UL)

PLLCTL_PLL_STATUS_ENABLE_SHIFT

#define PLLCTL_PLL_STATUS_ENABLE_SHIFT   (27U)

PLLCTL_PLL_STATUS_PLL_LOCK_COMB_GET

#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT)

PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK

#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK   (0x2U)

PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT

#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT   (1U)

PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_GET

#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT)

PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK

#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK   (0x1U)

PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT

#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT   (0U)

PLLCTL_PLL_STATUS_RESPONSE_GET

#define PLLCTL_PLL_STATUS_RESPONSE_GET

(

x

)

(((uint32_t)(x) & PLLCTL_PLL_STATUS_RESPONSE_MASK) >> PLLCTL_PLL_STATUS_RESPONSE_SHIFT)

PLLCTL_PLL_STATUS_RESPONSE_MASK

#define PLLCTL_PLL_STATUS_RESPONSE_MASK   (0x4U)

PLLCTL_PLL_STATUS_RESPONSE_SHIFT

#define PLLCTL_PLL_STATUS_RESPONSE_SHIFT   (2U)

PLLCTL_XTAL_ENABLE_GET

#define PLLCTL_XTAL_ENABLE_GET

(

x

)

(((uint32_t)(x) & PLLCTL_XTAL_ENABLE_MASK) >> PLLCTL_XTAL_ENABLE_SHIFT)

PLLCTL_XTAL_ENABLE_MASK

#define PLLCTL_XTAL_ENABLE_MASK   (0x10000000UL)

PLLCTL_XTAL_ENABLE_SHIFT

#define PLLCTL_XTAL_ENABLE_SHIFT   (28U)

PLLCTL_XTAL_RAMP_TIME_GET

#define PLLCTL_XTAL_RAMP_TIME_GET

(

x

)

(((uint32_t)(x) & PLLCTL_XTAL_RAMP_TIME_MASK) >> PLLCTL_XTAL_RAMP_TIME_SHIFT)

PLLCTL_XTAL_RAMP_TIME_MASK

#define PLLCTL_XTAL_RAMP_TIME_MASK   (0xFFFFFUL)

PLLCTL_XTAL_RAMP_TIME_SET

#define PLLCTL_XTAL_RAMP_TIME_SET

(

x

)

(((uint32_t)(x) << PLLCTL_XTAL_RAMP_TIME_SHIFT) & PLLCTL_XTAL_RAMP_TIME_MASK)

PLLCTL_XTAL_RAMP_TIME_SHIFT

#define PLLCTL_XTAL_RAMP_TIME_SHIFT   (0U)

PLLCTL_XTAL_RESPONSE_GET

#define PLLCTL_XTAL_RESPONSE_GET

(

x

)

(((uint32_t)(x) & PLLCTL_XTAL_RESPONSE_MASK) >> PLLCTL_XTAL_RESPONSE_SHIFT)

PLLCTL_XTAL_RESPONSE_MASK

#define PLLCTL_XTAL_RESPONSE_MASK   (0x20000000UL)

PLLCTL_XTAL_RESPONSE_SHIFT

#define PLLCTL_XTAL_RESPONSE_SHIFT   (29U)