hpm_pllctlv2_drv.h

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/*
 * Copyright (c) 2022-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_PLLCTLV2_DRV_H
#define HPM_PLLCTLV2_DRV_H
 
 
#include "hpm_common.h"
#include "hpm_soc_feature.h"
#include "hpm_pllctlv2_regs.h"
 
#define PLLCTLV2_CLK_SRC_XTAL24M (0U)
#define PLLCTLV2_CLK_SRC_IRC24M (1U)
 
static inline bool pllctlv2_xtal_is_stable(PLLCTLV2_Type *ptr)
{
    return IS_HPM_BITMASK_SET(ptr->XTAL, PLLCTLV2_XTAL_RESPONSE_MASK);
}
 
static inline bool pllctlv2_xtal_is_enabled(PLLCTLV2_Type *ptr)
{
    return IS_HPM_BITMASK_SET(ptr->XTAL, PLLCTLV2_XTAL_ENABLE_MASK);
}
 
static inline void pllctlv2_xtal_set_rampup_time(PLLCTLV2_Type *ptr, uint32_t rc24m_cycles)
{
    ptr->XTAL = (ptr->XTAL & ~PLLCTLV2_XTAL_RAMP_TIME_MASK) | PLLCTLV2_XTAL_RAMP_TIME_SET(rc24m_cycles);
}
 
static inline bool pllctlv2_pll_is_stable(PLLCTLV2_Type *ptr, uint8_t pll)
{
    return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_RESPONSE_MASK);
}
 
static inline bool pllctlv2_pll_is_enabled(PLLCTLV2_Type *ptr, uint8_t pll)
{
    return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_ENABLE_MASK);
}
 
static inline void pllctlv2_select_reference_clock(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t src)
{
    ptr->PLL[pll].CONFIG = (ptr->PLL[pll].CONFIG & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) | PLLCTLV2_PLL_CONFIG_REFSEL_SET(src);
}
 
void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop);
 
static inline void pllctlv2_disable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll)
{
    ptr->PLL[pll].CONFIG &= ~PLLCTLV2_PLL_CONFIG_SPREAD_MASK;
}
 
static inline void pllctlv2_set_pll_lock_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles)
{
    ptr->PLL[pll].LOCKTIME = PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(xtal_cycles);
}
 
static inline void pllctlv2_set_pll_step_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles)
{
    ptr->PLL[pll].STEPTIME = PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(xtal_cycles);
}
 
void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll,  uint8_t div_index, uint8_t div_value);
 
hpm_stat_t pllctlv2_set_pll_with_mfi_mfn(PLLCTLV2_Type *ptr, uint8_t pll,  uint32_t mfi, uint32_t mfn);
 
hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz);
 
uint32_t pllctlv2_get_pll_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll);
 
uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index);
 
 
#endif /* HPM_PLLCTLV2_DRV_H */