HPM SDK
HPMicro Software Development Kit
Data Structures | Macros
hpm_pwmv2_regs.h File Reference

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Data Structures

struct  PWMV2_Type
 

Macros

#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK   (0x80000000UL)
 
#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT   (31U)
 
#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SET(x)   (((uint32_t)(x) << PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK)
 
#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_GET(x)   (((uint32_t)(x) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK) >> PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT)
 
#define PWMV2_UNLOCK_UNLOCK_BIT_MASK   (0xFFFFFFFFUL)
 
#define PWMV2_UNLOCK_UNLOCK_BIT_SHIFT   (0U)
 
#define PWMV2_UNLOCK_UNLOCK_BIT_SET(x)   (((uint32_t)(x) << PWMV2_UNLOCK_UNLOCK_BIT_SHIFT) & PWMV2_UNLOCK_UNLOCK_BIT_MASK)
 
#define PWMV2_UNLOCK_UNLOCK_BIT_GET(x)   (((uint32_t)(x) & PWMV2_UNLOCK_UNLOCK_BIT_MASK) >> PWMV2_UNLOCK_UNLOCK_BIT_SHIFT)
 
#define PWMV2_SHADOW_VAL_VALUE_MASK   (0xFFFFFFFFUL)
 
#define PWMV2_SHADOW_VAL_VALUE_SHIFT   (0U)
 
#define PWMV2_SHADOW_VAL_VALUE_SET(x)   (((uint32_t)(x) << PWMV2_SHADOW_VAL_VALUE_SHIFT) & PWMV2_SHADOW_VAL_VALUE_MASK)
 
#define PWMV2_SHADOW_VAL_VALUE_GET(x)   (((uint32_t)(x) & PWMV2_SHADOW_VAL_VALUE_MASK) >> PWMV2_SHADOW_VAL_VALUE_SHIFT)
 
#define PWMV2_FORCE_MODE_POLARITY_MASK   (0xFF0000UL)
 
#define PWMV2_FORCE_MODE_POLARITY_SHIFT   (16U)
 
#define PWMV2_FORCE_MODE_POLARITY_SET(x)   (((uint32_t)(x) << PWMV2_FORCE_MODE_POLARITY_SHIFT) & PWMV2_FORCE_MODE_POLARITY_MASK)
 
#define PWMV2_FORCE_MODE_POLARITY_GET(x)   (((uint32_t)(x) & PWMV2_FORCE_MODE_POLARITY_MASK) >> PWMV2_FORCE_MODE_POLARITY_SHIFT)
 
#define PWMV2_FORCE_MODE_FORCE_MODE_MASK   (0xFFFFU)
 
#define PWMV2_FORCE_MODE_FORCE_MODE_SHIFT   (0U)
 
#define PWMV2_FORCE_MODE_FORCE_MODE_SET(x)   (((uint32_t)(x) << PWMV2_FORCE_MODE_FORCE_MODE_SHIFT) & PWMV2_FORCE_MODE_FORCE_MODE_MASK)
 
#define PWMV2_FORCE_MODE_FORCE_MODE_GET(x)   (((uint32_t)(x) & PWMV2_FORCE_MODE_FORCE_MODE_MASK) >> PWMV2_FORCE_MODE_FORCE_MODE_SHIFT)
 
#define PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK   (0x80000000UL)
 
#define PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT   (31U)
 
#define PWMV2_WORK_CTRL1_SHADOW_LOCK_SET(x)   (((uint32_t)(x) << PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK)
 
#define PWMV2_WORK_CTRL1_SHADOW_LOCK_GET(x)   (((uint32_t)(x) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK) >> PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT)
 
#define PWMV2_PWM_CFG0_TRIG_SEL4_MASK   (0x1000000UL)
 
#define PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT   (24U)
 
#define PWMV2_PWM_CFG0_TRIG_SEL4_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK)
 
#define PWMV2_PWM_CFG0_TRIG_SEL4_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK) >> PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT)
 
#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK   (0xF00U)
 
#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT   (8U)
 
#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK)
 
#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT)
 
#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK   (0x40U)
 
#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT   (6U)
 
#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK)
 
#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT)
 
#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK   (0x20U)
 
#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT   (5U)
 
#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK)
 
#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT)
 
#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK   (0x10U)
 
#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT   (4U)
 
#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK)
 
#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT)
 
#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK   (0x4U)
 
#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT   (2U)
 
#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK)
 
#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK) >> PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT)
 
#define PWMV2_PWM_CFG0_OUT_POLARITY_MASK   (0x2U)
 
#define PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT   (1U)
 
#define PWMV2_PWM_CFG0_OUT_POLARITY_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK)
 
#define PWMV2_PWM_CFG0_OUT_POLARITY_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK) >> PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT)
 
#define PWMV2_PWM_CFG0_POLARITY_OPT0_MASK   (0x1U)
 
#define PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT   (0U)
 
#define PWMV2_PWM_CFG0_POLARITY_OPT0_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK)
 
#define PWMV2_PWM_CFG0_POLARITY_OPT0_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK) >> PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT)
 
#define PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK   (0x10000000UL)
 
#define PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT   (28U)
 
#define PWMV2_PWM_CFG1_HIGHZ_EN_N_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK)
 
#define PWMV2_PWM_CFG1_HIGHZ_EN_N_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK) >> PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT)
 
#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK   (0xC000000UL)
 
#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT   (26U)
 
#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK)
 
#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT)
 
#define PWMV2_PWM_CFG1_FAULT_MODE_MASK   (0x3000000UL)
 
#define PWMV2_PWM_CFG1_FAULT_MODE_SHIFT   (24U)
 
#define PWMV2_PWM_CFG1_FAULT_MODE_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_MODE_SHIFT) & PWMV2_PWM_CFG1_FAULT_MODE_MASK)
 
#define PWMV2_PWM_CFG1_FAULT_MODE_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_MODE_MASK) >> PWMV2_PWM_CFG1_FAULT_MODE_SHIFT)
 
#define PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK   (0xC00000UL)
 
#define PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT   (22U)
 
#define PWMV2_PWM_CFG1_FAULT_REC_TIME_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK)
 
#define PWMV2_PWM_CFG1_FAULT_REC_TIME_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT)
 
#define PWMV2_PWM_CFG1_SW_FORCE_EN_MASK   (0x200000UL)
 
#define PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT   (21U)
 
#define PWMV2_PWM_CFG1_SW_FORCE_EN_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK)
 
#define PWMV2_PWM_CFG1_SW_FORCE_EN_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK) >> PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT)
 
#define PWMV2_PWM_CFG1_PAIR_MODE_MASK   (0x100000UL)
 
#define PWMV2_PWM_CFG1_PAIR_MODE_SHIFT   (20U)
 
#define PWMV2_PWM_CFG1_PAIR_MODE_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_PAIR_MODE_SHIFT) & PWMV2_PWM_CFG1_PAIR_MODE_MASK)
 
#define PWMV2_PWM_CFG1_PAIR_MODE_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_PAIR_MODE_MASK) >> PWMV2_PWM_CFG1_PAIR_MODE_SHIFT)
 
#define PWMV2_PWM_CFG1_PWM_LOGIC_MASK   (0xC0000UL)
 
#define PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT   (18U)
 
#define PWMV2_PWM_CFG1_PWM_LOGIC_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK)
 
#define PWMV2_PWM_CFG1_PWM_LOGIC_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK) >> PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT)
 
#define PWMV2_PWM_CFG1_FORCE_TIME_MASK   (0x30000UL)
 
#define PWMV2_PWM_CFG1_FORCE_TIME_SHIFT   (16U)
 
#define PWMV2_PWM_CFG1_FORCE_TIME_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_TIME_MASK)
 
#define PWMV2_PWM_CFG1_FORCE_TIME_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_TIME_SHIFT)
 
#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK   (0x7000U)
 
#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT   (12U)
 
#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK)
 
#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT)
 
#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK   (0x700U)
 
#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT   (8U)
 
#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK)
 
#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT)
 
#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK   (0x70U)
 
#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT   (4U)
 
#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK)
 
#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK) >> PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT)
 
#define PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK   (0x7U)
 
#define PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT   (0U)
 
#define PWMV2_PWM_CFG1_FAULT_REC_SEL_SET(x)   (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK)
 
#define PWMV2_PWM_CFG1_FAULT_REC_SEL_GET(x)   (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT)
 
#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK   (0xFFFFFFUL)
 
#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT   (0U)
 
#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SET(x)   (((uint32_t)(x) << PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK)
 
#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_GET(x)   (((uint32_t)(x) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK) >> PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT)
 
#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK   (0x1FU)
 
#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT   (0U)
 
#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SET(x)   (((uint32_t)(x) << PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK)
 
#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_GET(x)   (((uint32_t)(x) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK) >> PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT)
 
#define PWMV2_GLB_CTRL_SW_FORCE_MASK   (0xFF0000UL)
 
#define PWMV2_GLB_CTRL_SW_FORCE_SHIFT   (16U)
 
#define PWMV2_GLB_CTRL_SW_FORCE_SET(x)   (((uint32_t)(x) << PWMV2_GLB_CTRL_SW_FORCE_SHIFT) & PWMV2_GLB_CTRL_SW_FORCE_MASK)
 
#define PWMV2_GLB_CTRL_SW_FORCE_GET(x)   (((uint32_t)(x) & PWMV2_GLB_CTRL_SW_FORCE_MASK) >> PWMV2_GLB_CTRL_SW_FORCE_SHIFT)
 
#define PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK   (0x300U)
 
#define PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT   (8U)
 
#define PWMV2_GLB_CTRL_OUTPUT_DELAY_SET(x)   (((uint32_t)(x) << PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK)
 
#define PWMV2_GLB_CTRL_OUTPUT_DELAY_GET(x)   (((uint32_t)(x) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK) >> PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT)
 
#define PWMV2_GLB_CTRL_HR_PWM_EN_MASK   (0x10U)
 
#define PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT   (4U)
 
#define PWMV2_GLB_CTRL_HR_PWM_EN_SET(x)   (((uint32_t)(x) << PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK)
 
#define PWMV2_GLB_CTRL_HR_PWM_EN_GET(x)   (((uint32_t)(x) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK) >> PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT)
 
#define PWMV2_GLB_CTRL_FRAC_DISABLE_MASK   (0x8U)
 
#define PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT   (3U)
 
#define PWMV2_GLB_CTRL_FRAC_DISABLE_SET(x)   (((uint32_t)(x) << PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK)
 
#define PWMV2_GLB_CTRL_FRAC_DISABLE_GET(x)   (((uint32_t)(x) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK) >> PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT)
 
#define PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK   (0xF000000UL)
 
#define PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT   (24U)
 
#define PWMV2_GLB_CTRL2_DAC_SW_MODE_SET(x)   (((uint32_t)(x) << PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK)
 
#define PWMV2_GLB_CTRL2_DAC_SW_MODE_GET(x)   (((uint32_t)(x) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK) >> PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT)
 
#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK   (0x200000UL)
 
#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT   (21U)
 
#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SET(x)   (((uint32_t)(x) << PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK)
 
#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_GET(x)   (((uint32_t)(x) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK) >> PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT)
 
#define PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK   (0xFF00U)
 
#define PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT   (8U)
 
#define PWMV2_GLB_CTRL2_FAULT_CLEAR_SET(x)   (((uint32_t)(x) << PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK)
 
#define PWMV2_GLB_CTRL2_FAULT_CLEAR_GET(x)   (((uint32_t)(x) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK) >> PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT)
 
#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK   (0x1U)
 
#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT   (0U)
 
#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SET(x)   (((uint32_t)(x) << PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK)
 
#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_GET(x)   (((uint32_t)(x) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK) >> PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT)
 
#define PWMV2_CNT_RELOAD_WORK_VALUE_MASK   (0xFFFFFFFFUL)
 
#define PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT   (0U)
 
#define PWMV2_CNT_RELOAD_WORK_VALUE_GET(x)   (((uint32_t)(x) & PWMV2_CNT_RELOAD_WORK_VALUE_MASK) >> PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT)
 
#define PWMV2_CMP_VAL_WORK_VALUE_MASK   (0xFFFFFFFFUL)
 
#define PWMV2_CMP_VAL_WORK_VALUE_SHIFT   (0U)
 
#define PWMV2_CMP_VAL_WORK_VALUE_GET(x)   (((uint32_t)(x) & PWMV2_CMP_VAL_WORK_VALUE_MASK) >> PWMV2_CMP_VAL_WORK_VALUE_SHIFT)
 
#define PWMV2_FORCE_WORK_OUT_POLARITY_MASK   (0xFF0000UL)
 
#define PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT   (16U)
 
#define PWMV2_FORCE_WORK_OUT_POLARITY_GET(x)   (((uint32_t)(x) & PWMV2_FORCE_WORK_OUT_POLARITY_MASK) >> PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT)
 
#define PWMV2_FORCE_WORK_FORCE_MODE_MASK   (0xFFFFU)
 
#define PWMV2_FORCE_WORK_FORCE_MODE_SHIFT   (0U)
 
#define PWMV2_FORCE_WORK_FORCE_MODE_GET(x)   (((uint32_t)(x) & PWMV2_FORCE_WORK_FORCE_MODE_MASK) >> PWMV2_FORCE_WORK_FORCE_MODE_SHIFT)
 
#define PWMV2_CNT_VAL_VALUE_MASK   (0xFFFFFFFFUL)
 
#define PWMV2_CNT_VAL_VALUE_SHIFT   (0U)
 
#define PWMV2_CNT_VAL_VALUE_GET(x)   (((uint32_t)(x) & PWMV2_CNT_VAL_VALUE_MASK) >> PWMV2_CNT_VAL_VALUE_SHIFT)
 
#define PWMV2_DAC_VALUE_SV_VALUE_MASK   (0xFFFFFFFFUL)
 
#define PWMV2_DAC_VALUE_SV_VALUE_SHIFT   (0U)
 
#define PWMV2_DAC_VALUE_SV_VALUE_SET(x)   (((uint32_t)(x) << PWMV2_DAC_VALUE_SV_VALUE_SHIFT) & PWMV2_DAC_VALUE_SV_VALUE_MASK)
 
#define PWMV2_DAC_VALUE_SV_VALUE_GET(x)   (((uint32_t)(x) & PWMV2_DAC_VALUE_SV_VALUE_MASK) >> PWMV2_DAC_VALUE_SV_VALUE_SHIFT)
 
#define PWMV2_CAPTURE_POS_CAPTURE_POS_MASK   (0xFFFFFF00UL)
 
#define PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT   (8U)
 
#define PWMV2_CAPTURE_POS_CAPTURE_POS_GET(x)   (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_POS_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT)
 
#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK   (0x10U)
 
#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT   (4U)
 
#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SET(x)   (((uint32_t)(x) << PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK)
 
#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_GET(x)   (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT)
 
#define PWMV2_CAPTURE_POS_CNT_INDEX_MASK   (0x3U)
 
#define PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT   (0U)
 
#define PWMV2_CAPTURE_POS_CNT_INDEX_SET(x)   (((uint32_t)(x) << PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK)
 
#define PWMV2_CAPTURE_POS_CNT_INDEX_GET(x)   (((uint32_t)(x) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK) >> PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT)
 
#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK   (0xFFFFFF00UL)
 
#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT   (8U)
 
#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_GET(x)   (((uint32_t)(x) & PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK) >> PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT)
 
#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK   (0x80000000UL)
 
#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT   (31U)
 
#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK)
 
#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK) >> PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT)
 
#define PWMV2_IRQ_STS_IRQ_BURSTEND_MASK   (0x20U)
 
#define PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT   (5U)
 
#define PWMV2_IRQ_STS_IRQ_BURSTEND_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_BURSTEND_MASK) >> PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT)
 
#define PWMV2_IRQ_STS_IRQ_FAULT_MASK   (0x10U)
 
#define PWMV2_IRQ_STS_IRQ_FAULT_SHIFT   (4U)
 
#define PWMV2_IRQ_STS_IRQ_FAULT_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_FAULT_MASK) >> PWMV2_IRQ_STS_IRQ_FAULT_SHIFT)
 
#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK   (0x8U)
 
#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT   (3U)
 
#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT)
 
#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK   (0x4U)
 
#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT   (2U)
 
#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT)
 
#define PWMV2_IRQ_STS_IRQ_RELOAD_MASK   (0x2U)
 
#define PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT   (1U)
 
#define PWMV2_IRQ_STS_IRQ_RELOAD_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_RELOAD_MASK) >> PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT)
 
#define PWMV2_IRQ_STS_IRQ_CMP_MASK   (0x1U)
 
#define PWMV2_IRQ_STS_IRQ_CMP_SHIFT   (0U)
 
#define PWMV2_IRQ_STS_IRQ_CMP_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CMP_MASK) >> PWMV2_IRQ_STS_IRQ_CMP_SHIFT)
 
#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK   (0x80000000UL)
 
#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT   (31U)
 
#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK)
 
#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK) >> PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT)
 
#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK   (0xFFFFFFUL)
 
#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT   (0U)
 
#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK)
 
#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK) >> PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT)
 
#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK   (0xFU)
 
#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT   (0U)
 
#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK)
 
#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK) >> PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT)
 
#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK   (0xFFU)
 
#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT   (0U)
 
#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK)
 
#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK) >> PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT)
 
#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK   (0xFFU)
 
#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT   (0U)
 
#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK)
 
#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK) >> PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT)
 
#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK   (0xFFU)
 
#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT   (0U)
 
#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK)
 
#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK) >> PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT)
 
#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK   (0xFU)
 
#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT   (0U)
 
#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK)
 
#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK) >> PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT)
 
#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK   (0xFFFFFFUL)
 
#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT   (0U)
 
#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK)
 
#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK) >> PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT)
 
#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK   (0xFU)
 
#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT   (0U)
 
#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK)
 
#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK) >> PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT)
 
#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK   (0xFFU)
 
#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT   (0U)
 
#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK)
 
#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK) >> PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT)
 
#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK   (0xFFU)
 
#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT   (0U)
 
#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK)
 
#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK) >> PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT)
 
#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK   (0xFFU)
 
#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT   (0U)
 
#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK)
 
#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK) >> PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT)
 
#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK   (0xFU)
 
#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT   (0U)
 
#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SET(x)   (((uint32_t)(x) << PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK)
 
#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_GET(x)   (((uint32_t)(x) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK) >> PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT)
 
#define PWMV2_DMA_EN_DMA3_EN_MASK   (0x80000000UL)
 
#define PWMV2_DMA_EN_DMA3_EN_SHIFT   (31U)
 
#define PWMV2_DMA_EN_DMA3_EN_SET(x)   (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_EN_SHIFT) & PWMV2_DMA_EN_DMA3_EN_MASK)
 
#define PWMV2_DMA_EN_DMA3_EN_GET(x)   (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_EN_MASK) >> PWMV2_DMA_EN_DMA3_EN_SHIFT)
 
#define PWMV2_DMA_EN_DMA3_SEL_MASK   (0x1F000000UL)
 
#define PWMV2_DMA_EN_DMA3_SEL_SHIFT   (24U)
 
#define PWMV2_DMA_EN_DMA3_SEL_SET(x)   (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_SEL_SHIFT) & PWMV2_DMA_EN_DMA3_SEL_MASK)
 
#define PWMV2_DMA_EN_DMA3_SEL_GET(x)   (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_SEL_MASK) >> PWMV2_DMA_EN_DMA3_SEL_SHIFT)
 
#define PWMV2_DMA_EN_DMA2_EN_MASK   (0x800000UL)
 
#define PWMV2_DMA_EN_DMA2_EN_SHIFT   (23U)
 
#define PWMV2_DMA_EN_DMA2_EN_SET(x)   (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_EN_SHIFT) & PWMV2_DMA_EN_DMA2_EN_MASK)
 
#define PWMV2_DMA_EN_DMA2_EN_GET(x)   (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_EN_MASK) >> PWMV2_DMA_EN_DMA2_EN_SHIFT)
 
#define PWMV2_DMA_EN_DMA2_SEL_MASK   (0x1F0000UL)
 
#define PWMV2_DMA_EN_DMA2_SEL_SHIFT   (16U)
 
#define PWMV2_DMA_EN_DMA2_SEL_SET(x)   (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_SEL_SHIFT) & PWMV2_DMA_EN_DMA2_SEL_MASK)
 
#define PWMV2_DMA_EN_DMA2_SEL_GET(x)   (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_SEL_MASK) >> PWMV2_DMA_EN_DMA2_SEL_SHIFT)
 
#define PWMV2_DMA_EN_DMA1_EN_MASK   (0x8000U)
 
#define PWMV2_DMA_EN_DMA1_EN_SHIFT   (15U)
 
#define PWMV2_DMA_EN_DMA1_EN_SET(x)   (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_EN_SHIFT) & PWMV2_DMA_EN_DMA1_EN_MASK)
 
#define PWMV2_DMA_EN_DMA1_EN_GET(x)   (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_EN_MASK) >> PWMV2_DMA_EN_DMA1_EN_SHIFT)
 
#define PWMV2_DMA_EN_DMA1_SEL_MASK   (0x1F00U)
 
#define PWMV2_DMA_EN_DMA1_SEL_SHIFT   (8U)
 
#define PWMV2_DMA_EN_DMA1_SEL_SET(x)   (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_SEL_SHIFT) & PWMV2_DMA_EN_DMA1_SEL_MASK)
 
#define PWMV2_DMA_EN_DMA1_SEL_GET(x)   (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_SEL_MASK) >> PWMV2_DMA_EN_DMA1_SEL_SHIFT)
 
#define PWMV2_DMA_EN_DMA0_EN_MASK   (0x80U)
 
#define PWMV2_DMA_EN_DMA0_EN_SHIFT   (7U)
 
#define PWMV2_DMA_EN_DMA0_EN_SET(x)   (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_EN_SHIFT) & PWMV2_DMA_EN_DMA0_EN_MASK)
 
#define PWMV2_DMA_EN_DMA0_EN_GET(x)   (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_EN_MASK) >> PWMV2_DMA_EN_DMA0_EN_SHIFT)
 
#define PWMV2_DMA_EN_DMA0_SEL_MASK   (0x1FU)
 
#define PWMV2_DMA_EN_DMA0_SEL_SHIFT   (0U)
 
#define PWMV2_DMA_EN_DMA0_SEL_SET(x)   (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_SEL_SHIFT) & PWMV2_DMA_EN_DMA0_SEL_MASK)
 
#define PWMV2_DMA_EN_DMA0_SEL_GET(x)   (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_SEL_MASK) >> PWMV2_DMA_EN_DMA0_SEL_SHIFT)
 
#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK   (0x1F000000UL)
 
#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT   (24U)
 
#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK)
 
#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT)
 
#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK   (0x1F0000UL)
 
#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT   (16U)
 
#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK)
 
#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT)
 
#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK   (0x7000U)
 
#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT   (12U)
 
#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK)
 
#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK) >> PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT)
 
#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK   (0x300U)
 
#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT   (8U)
 
#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK)
 
#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK) >> PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT)
 
#define PWMV2_CNT_CFG0_CNT_D_PARAM_MASK   (0x1FU)
 
#define PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT   (0U)
 
#define PWMV2_CNT_CFG0_CNT_D_PARAM_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK)
 
#define PWMV2_CNT_CFG0_CNT_D_PARAM_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK) >> PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT)
 
#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK   (0x3000000UL)
 
#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT   (24U)
 
#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK)
 
#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK) >> PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT)
 
#define PWMV2_CNT_CFG1_CNT_LU_EN_MASK   (0x800000UL)
 
#define PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT   (23U)
 
#define PWMV2_CNT_CFG1_CNT_LU_EN_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK)
 
#define PWMV2_CNT_CFG1_CNT_LU_EN_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT)
 
#define PWMV2_CNT_CFG1_CNT_LIM_UP_MASK   (0x1F0000UL)
 
#define PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT   (16U)
 
#define PWMV2_CNT_CFG1_CNT_LIM_UP_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK)
 
#define PWMV2_CNT_CFG1_CNT_LIM_UP_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT)
 
#define PWMV2_CNT_CFG1_CNT_LL_EN_MASK   (0x8000U)
 
#define PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT   (15U)
 
#define PWMV2_CNT_CFG1_CNT_LL_EN_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK)
 
#define PWMV2_CNT_CFG1_CNT_LL_EN_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT)
 
#define PWMV2_CNT_CFG1_CNT_LIM_LO_MASK   (0x1F00U)
 
#define PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT   (8U)
 
#define PWMV2_CNT_CFG1_CNT_LIM_LO_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK)
 
#define PWMV2_CNT_CFG1_CNT_LIM_LO_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT)
 
#define PWMV2_CNT_CFG1_CNT_IN_OFF_MASK   (0x1FU)
 
#define PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT   (0U)
 
#define PWMV2_CNT_CFG1_CNT_IN_OFF_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK)
 
#define PWMV2_CNT_CFG1_CNT_IN_OFF_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK) >> PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT)
 
#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK   (0x80000000UL)
 
#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT   (31U)
 
#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK)
 
#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT)
 
#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK   (0x7000000UL)
 
#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT   (24U)
 
#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK)
 
#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK   (0x700000UL)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT   (20U)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK   (0x80000UL)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT   (19U)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT)
 
#define PWMV2_CNT_CFG2_CNT_TRIG1_MASK   (0xF000U)
 
#define PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT   (12U)
 
#define PWMV2_CNT_CFG2_CNT_TRIG1_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK)
 
#define PWMV2_CNT_CFG2_CNT_TRIG1_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK   (0x700U)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT   (8U)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK   (0x80U)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT   (7U)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK)
 
#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT)
 
#define PWMV2_CNT_CFG2_CNT_TRIG0_MASK   (0xFU)
 
#define PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT   (0U)
 
#define PWMV2_CNT_CFG2_CNT_TRIG0_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK)
 
#define PWMV2_CNT_CFG2_CNT_TRIG0_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT)
 
#define PWMV2_CNT_CFG3_CNT_START_SEL_MASK   (0x700000UL)
 
#define PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT   (20U)
 
#define PWMV2_CNT_CFG3_CNT_START_SEL_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK)
 
#define PWMV2_CNT_CFG3_CNT_START_SEL_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK) >> PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT)
 
#define PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK   (0x20000UL)
 
#define PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT   (17U)
 
#define PWMV2_CNT_CFG3_CNT_HW_START_EN_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK)
 
#define PWMV2_CNT_CFG3_CNT_HW_START_EN_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK) >> PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT)
 
#define PWMV2_CNT_CFG3_CNT_BURST_MASK   (0xFFFFU)
 
#define PWMV2_CNT_CFG3_CNT_BURST_SHIFT   (0U)
 
#define PWMV2_CNT_CFG3_CNT_BURST_SET(x)   (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_BURST_SHIFT) & PWMV2_CNT_CFG3_CNT_BURST_MASK)
 
#define PWMV2_CNT_CFG3_CNT_BURST_GET(x)   (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_BURST_MASK) >> PWMV2_CNT_CFG3_CNT_BURST_SHIFT)
 
#define PWMV2_CNT_GLBCFG_CNT_SW_START_MASK   (0xF0000UL)
 
#define PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT   (16U)
 
#define PWMV2_CNT_GLBCFG_CNT_SW_START_SET(x)   (((uint32_t)(x) << PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK)
 
#define PWMV2_CNT_GLBCFG_CNT_SW_START_GET(x)   (((uint32_t)(x) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK) >> PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT)
 
#define PWMV2_CNT_GLBCFG_TIMER_RESET_MASK   (0xF00U)
 
#define PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT   (8U)
 
#define PWMV2_CNT_GLBCFG_TIMER_RESET_SET(x)   (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK)
 
#define PWMV2_CNT_GLBCFG_TIMER_RESET_GET(x)   (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK) >> PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT)
 
#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK   (0xFU)
 
#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT   (0U)
 
#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET(x)   (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK)
 
#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_GET(x)   (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK) >> PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT)
 
#define PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK   (0x1F000000UL)
 
#define PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT   (24U)
 
#define PWMV2_CAL_CFG0_CAL_LU_PARAM_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK)
 
#define PWMV2_CAL_CFG0_CAL_LU_PARAM_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT)
 
#define PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK   (0x1F0000UL)
 
#define PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT   (16U)
 
#define PWMV2_CAL_CFG0_CAL_LL_PARAM_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK)
 
#define PWMV2_CAL_CFG0_CAL_LL_PARAM_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT)
 
#define PWMV2_CAL_CFG0_CAL_T_PARAM_MASK   (0x1F00U)
 
#define PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT   (8U)
 
#define PWMV2_CAL_CFG0_CAL_T_PARAM_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK)
 
#define PWMV2_CAL_CFG0_CAL_T_PARAM_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT)
 
#define PWMV2_CAL_CFG0_CAL_D_PARAM_MASK   (0x1FU)
 
#define PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT   (0U)
 
#define PWMV2_CAL_CFG0_CAL_D_PARAM_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK)
 
#define PWMV2_CAL_CFG0_CAL_D_PARAM_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT)
 
#define PWMV2_CAL_CFG1_CAL_T_INDEX_MASK   (0x30000000UL)
 
#define PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT   (28U)
 
#define PWMV2_CAL_CFG1_CAL_T_INDEX_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK)
 
#define PWMV2_CAL_CFG1_CAL_T_INDEX_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT)
 
#define PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK   (0x7000000UL)
 
#define PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT   (24U)
 
#define PWMV2_CAL_CFG1_CAL_IN_INDEX_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK)
 
#define PWMV2_CAL_CFG1_CAL_IN_INDEX_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT)
 
#define PWMV2_CAL_CFG1_CAL_LU_EN_MASK   (0x800000UL)
 
#define PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT   (23U)
 
#define PWMV2_CAL_CFG1_CAL_LU_EN_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK)
 
#define PWMV2_CAL_CFG1_CAL_LU_EN_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT)
 
#define PWMV2_CAL_CFG1_CAL_LIM_UP_MASK   (0x1F0000UL)
 
#define PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT   (16U)
 
#define PWMV2_CAL_CFG1_CAL_LIM_UP_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK)
 
#define PWMV2_CAL_CFG1_CAL_LIM_UP_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT)
 
#define PWMV2_CAL_CFG1_CAL_LL_EN_MASK   (0x8000U)
 
#define PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT   (15U)
 
#define PWMV2_CAL_CFG1_CAL_LL_EN_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK)
 
#define PWMV2_CAL_CFG1_CAL_LL_EN_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT)
 
#define PWMV2_CAL_CFG1_CAL_LIM_LO_MASK   (0x1F00U)
 
#define PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT   (8U)
 
#define PWMV2_CAL_CFG1_CAL_LIM_LO_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK)
 
#define PWMV2_CAL_CFG1_CAL_LIM_LO_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT)
 
#define PWMV2_CAL_CFG1_CAL_IN_OFF_MASK   (0x1FU)
 
#define PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT   (0U)
 
#define PWMV2_CAL_CFG1_CAL_IN_OFF_SET(x)   (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK)
 
#define PWMV2_CAL_CFG1_CAL_IN_OFF_GET(x)   (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK) >> PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT)
 
#define PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK   (0x70000000UL)
 
#define PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT   (28U)
 
#define PWMV2_CMP_CFG_CMP_TRIG_SEL_SET(x)   (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK)
 
#define PWMV2_CMP_CFG_CMP_TRIG_SEL_GET(x)   (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK) >> PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT)
 
#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK   (0x7000000UL)
 
#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT   (24U)
 
#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SET(x)   (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK)
 
#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_GET(x)   (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK) >> PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT)
 
#define PWMV2_CMP_CFG_CMP_IN_SEL_MASK   (0x3F0000UL)
 
#define PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT   (16U)
 
#define PWMV2_CMP_CFG_CMP_IN_SEL_SET(x)   (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK)
 
#define PWMV2_CMP_CFG_CMP_IN_SEL_GET(x)   (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK) >> PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT)
 
#define PWMV2_CMP_CFG_CMP_CNT_MASK   (0xC000U)
 
#define PWMV2_CMP_CFG_CMP_CNT_SHIFT   (14U)
 
#define PWMV2_CMP_CFG_CMP_CNT_SET(x)   (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_CNT_SHIFT) & PWMV2_CMP_CFG_CMP_CNT_MASK)
 
#define PWMV2_CMP_CFG_CMP_CNT_GET(x)   (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_CNT_MASK) >> PWMV2_CMP_CFG_CMP_CNT_SHIFT)
 
#define PWMV2_SHADOW_VAL_0   (0UL)
 
#define PWMV2_SHADOW_VAL_1   (1UL)
 
#define PWMV2_SHADOW_VAL_2   (2UL)
 
#define PWMV2_SHADOW_VAL_3   (3UL)
 
#define PWMV2_SHADOW_VAL_4   (4UL)
 
#define PWMV2_SHADOW_VAL_5   (5UL)
 
#define PWMV2_SHADOW_VAL_6   (6UL)
 
#define PWMV2_SHADOW_VAL_7   (7UL)
 
#define PWMV2_SHADOW_VAL_8   (8UL)
 
#define PWMV2_SHADOW_VAL_9   (9UL)
 
#define PWMV2_SHADOW_VAL_10   (10UL)
 
#define PWMV2_SHADOW_VAL_11   (11UL)
 
#define PWMV2_SHADOW_VAL_12   (12UL)
 
#define PWMV2_SHADOW_VAL_13   (13UL)
 
#define PWMV2_SHADOW_VAL_14   (14UL)
 
#define PWMV2_SHADOW_VAL_15   (15UL)
 
#define PWMV2_SHADOW_VAL_16   (16UL)
 
#define PWMV2_SHADOW_VAL_17   (17UL)
 
#define PWMV2_SHADOW_VAL_18   (18UL)
 
#define PWMV2_SHADOW_VAL_19   (19UL)
 
#define PWMV2_SHADOW_VAL_20   (20UL)
 
#define PWMV2_SHADOW_VAL_21   (21UL)
 
#define PWMV2_SHADOW_VAL_22   (22UL)
 
#define PWMV2_SHADOW_VAL_23   (23UL)
 
#define PWMV2_SHADOW_VAL_24   (24UL)
 
#define PWMV2_SHADOW_VAL_25   (25UL)
 
#define PWMV2_SHADOW_VAL_26   (26UL)
 
#define PWMV2_SHADOW_VAL_27   (27UL)
 
#define PWMV2_PWM_0   (0UL)
 
#define PWMV2_PWM_1   (1UL)
 
#define PWMV2_PWM_2   (2UL)
 
#define PWMV2_PWM_3   (3UL)
 
#define PWMV2_PWM_4   (4UL)
 
#define PWMV2_PWM_5   (5UL)
 
#define PWMV2_PWM_6   (6UL)
 
#define PWMV2_PWM_7   (7UL)
 
#define PWMV2_TRIGGER_CFG_0   (0UL)
 
#define PWMV2_TRIGGER_CFG_1   (1UL)
 
#define PWMV2_TRIGGER_CFG_2   (2UL)
 
#define PWMV2_TRIGGER_CFG_3   (3UL)
 
#define PWMV2_TRIGGER_CFG_4   (4UL)
 
#define PWMV2_TRIGGER_CFG_5   (5UL)
 
#define PWMV2_TRIGGER_CFG_6   (6UL)
 
#define PWMV2_TRIGGER_CFG_7   (7UL)
 
#define PWMV2_CNT_RELOAD_WORK_0   (0UL)
 
#define PWMV2_CNT_RELOAD_WORK_1   (1UL)
 
#define PWMV2_CNT_RELOAD_WORK_2   (2UL)
 
#define PWMV2_CNT_RELOAD_WORK_3   (3UL)
 
#define PWMV2_CMP_VAL_WORK_0   (0UL)
 
#define PWMV2_CMP_VAL_WORK_1   (1UL)
 
#define PWMV2_CMP_VAL_WORK_2   (2UL)
 
#define PWMV2_CMP_VAL_WORK_3   (3UL)
 
#define PWMV2_CMP_VAL_WORK_4   (4UL)
 
#define PWMV2_CMP_VAL_WORK_5   (5UL)
 
#define PWMV2_CMP_VAL_WORK_6   (6UL)
 
#define PWMV2_CMP_VAL_WORK_7   (7UL)
 
#define PWMV2_CMP_VAL_WORK_8   (8UL)
 
#define PWMV2_CMP_VAL_WORK_9   (9UL)
 
#define PWMV2_CMP_VAL_WORK_10   (10UL)
 
#define PWMV2_CMP_VAL_WORK_11   (11UL)
 
#define PWMV2_CMP_VAL_WORK_12   (12UL)
 
#define PWMV2_CMP_VAL_WORK_13   (13UL)
 
#define PWMV2_CMP_VAL_WORK_14   (14UL)
 
#define PWMV2_CMP_VAL_WORK_15   (15UL)
 
#define PWMV2_CMP_VAL_WORK_16   (16UL)
 
#define PWMV2_CMP_VAL_WORK_17   (17UL)
 
#define PWMV2_CMP_VAL_WORK_18   (18UL)
 
#define PWMV2_CMP_VAL_WORK_19   (19UL)
 
#define PWMV2_CMP_VAL_WORK_20   (20UL)
 
#define PWMV2_CMP_VAL_WORK_21   (21UL)
 
#define PWMV2_CMP_VAL_WORK_22   (22UL)
 
#define PWMV2_CMP_VAL_WORK_23   (23UL)
 
#define PWMV2_CNT_VAL_0   (0UL)
 
#define PWMV2_CNT_VAL_1   (1UL)
 
#define PWMV2_CNT_VAL_2   (2UL)
 
#define PWMV2_CNT_VAL_3   (3UL)
 
#define PWMV2_DAC_VALUE_SV_0   (0UL)
 
#define PWMV2_DAC_VALUE_SV_1   (1UL)
 
#define PWMV2_DAC_VALUE_SV_2   (2UL)
 
#define PWMV2_DAC_VALUE_SV_3   (3UL)
 
#define PWMV2_CAPTURE_POS_0   (0UL)
 
#define PWMV2_CAPTURE_POS_1   (1UL)
 
#define PWMV2_CAPTURE_POS_2   (2UL)
 
#define PWMV2_CAPTURE_POS_3   (3UL)
 
#define PWMV2_CAPTURE_POS_4   (4UL)
 
#define PWMV2_CAPTURE_POS_5   (5UL)
 
#define PWMV2_CAPTURE_POS_6   (6UL)
 
#define PWMV2_CAPTURE_POS_7   (7UL)
 
#define PWMV2_CAPTURE_NEG_0   (0UL)
 
#define PWMV2_CAPTURE_NEG_1   (1UL)
 
#define PWMV2_CAPTURE_NEG_2   (2UL)
 
#define PWMV2_CAPTURE_NEG_3   (3UL)
 
#define PWMV2_CAPTURE_NEG_4   (4UL)
 
#define PWMV2_CAPTURE_NEG_5   (5UL)
 
#define PWMV2_CAPTURE_NEG_6   (6UL)
 
#define PWMV2_CAPTURE_NEG_7   (7UL)
 
#define PWMV2_CNT_0   (0UL)
 
#define PWMV2_CNT_1   (1UL)
 
#define PWMV2_CNT_2   (2UL)
 
#define PWMV2_CNT_3   (3UL)
 
#define PWMV2_CAL_0   (0UL)
 
#define PWMV2_CAL_1   (1UL)
 
#define PWMV2_CAL_2   (2UL)
 
#define PWMV2_CAL_3   (3UL)
 
#define PWMV2_CAL_4   (4UL)
 
#define PWMV2_CAL_5   (5UL)
 
#define PWMV2_CAL_6   (6UL)
 
#define PWMV2_CAL_7   (7UL)
 
#define PWMV2_CAL_8   (8UL)
 
#define PWMV2_CAL_9   (9UL)
 
#define PWMV2_CAL_10   (10UL)
 
#define PWMV2_CAL_11   (11UL)
 
#define PWMV2_CAL_12   (12UL)
 
#define PWMV2_CAL_13   (13UL)
 
#define PWMV2_CAL_14   (14UL)
 
#define PWMV2_CAL_15   (15UL)
 
#define PWMV2_CMP_0   (0UL)
 
#define PWMV2_CMP_1   (1UL)
 
#define PWMV2_CMP_2   (2UL)
 
#define PWMV2_CMP_3   (3UL)
 
#define PWMV2_CMP_4   (4UL)
 
#define PWMV2_CMP_5   (5UL)
 
#define PWMV2_CMP_6   (6UL)
 
#define PWMV2_CMP_7   (7UL)
 
#define PWMV2_CMP_8   (8UL)
 
#define PWMV2_CMP_9   (9UL)
 
#define PWMV2_CMP_10   (10UL)
 
#define PWMV2_CMP_11   (11UL)
 
#define PWMV2_CMP_12   (12UL)
 
#define PWMV2_CMP_13   (13UL)
 
#define PWMV2_CMP_14   (14UL)
 
#define PWMV2_CMP_15   (15UL)
 
#define PWMV2_CMP_16   (16UL)
 
#define PWMV2_CMP_17   (17UL)
 
#define PWMV2_CMP_18   (18UL)
 
#define PWMV2_CMP_19   (19UL)
 
#define PWMV2_CMP_20   (20UL)
 
#define PWMV2_CMP_21   (21UL)
 
#define PWMV2_CMP_22   (22UL)
 
#define PWMV2_CMP_23   (23UL)
 

Macro Definition Documentation

◆ PWMV2_CAL_0

#define PWMV2_CAL_0   (0UL)

◆ PWMV2_CAL_1

#define PWMV2_CAL_1   (1UL)

◆ PWMV2_CAL_10

#define PWMV2_CAL_10   (10UL)

◆ PWMV2_CAL_11

#define PWMV2_CAL_11   (11UL)

◆ PWMV2_CAL_12

#define PWMV2_CAL_12   (12UL)

◆ PWMV2_CAL_13

#define PWMV2_CAL_13   (13UL)

◆ PWMV2_CAL_14

#define PWMV2_CAL_14   (14UL)

◆ PWMV2_CAL_15

#define PWMV2_CAL_15   (15UL)

◆ PWMV2_CAL_2

#define PWMV2_CAL_2   (2UL)

◆ PWMV2_CAL_3

#define PWMV2_CAL_3   (3UL)

◆ PWMV2_CAL_4

#define PWMV2_CAL_4   (4UL)

◆ PWMV2_CAL_5

#define PWMV2_CAL_5   (5UL)

◆ PWMV2_CAL_6

#define PWMV2_CAL_6   (6UL)

◆ PWMV2_CAL_7

#define PWMV2_CAL_7   (7UL)

◆ PWMV2_CAL_8

#define PWMV2_CAL_8   (8UL)

◆ PWMV2_CAL_9

#define PWMV2_CAL_9   (9UL)

◆ PWMV2_CAL_CFG0_CAL_D_PARAM_GET

#define PWMV2_CAL_CFG0_CAL_D_PARAM_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT)

◆ PWMV2_CAL_CFG0_CAL_D_PARAM_MASK

#define PWMV2_CAL_CFG0_CAL_D_PARAM_MASK   (0x1FU)

◆ PWMV2_CAL_CFG0_CAL_D_PARAM_SET

#define PWMV2_CAL_CFG0_CAL_D_PARAM_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK)

◆ PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT

#define PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT   (0U)

◆ PWMV2_CAL_CFG0_CAL_LL_PARAM_GET

#define PWMV2_CAL_CFG0_CAL_LL_PARAM_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT)

◆ PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK

#define PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK   (0x1F0000UL)

◆ PWMV2_CAL_CFG0_CAL_LL_PARAM_SET

#define PWMV2_CAL_CFG0_CAL_LL_PARAM_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK)

◆ PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT

#define PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT   (16U)

◆ PWMV2_CAL_CFG0_CAL_LU_PARAM_GET

#define PWMV2_CAL_CFG0_CAL_LU_PARAM_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT)

◆ PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK

#define PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK   (0x1F000000UL)

◆ PWMV2_CAL_CFG0_CAL_LU_PARAM_SET

#define PWMV2_CAL_CFG0_CAL_LU_PARAM_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK)

◆ PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT

#define PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT   (24U)

◆ PWMV2_CAL_CFG0_CAL_T_PARAM_GET

#define PWMV2_CAL_CFG0_CAL_T_PARAM_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT)

◆ PWMV2_CAL_CFG0_CAL_T_PARAM_MASK

#define PWMV2_CAL_CFG0_CAL_T_PARAM_MASK   (0x1F00U)

◆ PWMV2_CAL_CFG0_CAL_T_PARAM_SET

#define PWMV2_CAL_CFG0_CAL_T_PARAM_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK)

◆ PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT

#define PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT   (8U)

◆ PWMV2_CAL_CFG1_CAL_IN_INDEX_GET

#define PWMV2_CAL_CFG1_CAL_IN_INDEX_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT)

◆ PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK

#define PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK   (0x7000000UL)

◆ PWMV2_CAL_CFG1_CAL_IN_INDEX_SET

#define PWMV2_CAL_CFG1_CAL_IN_INDEX_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK)

◆ PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT

#define PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT   (24U)

◆ PWMV2_CAL_CFG1_CAL_IN_OFF_GET

#define PWMV2_CAL_CFG1_CAL_IN_OFF_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK) >> PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT)

◆ PWMV2_CAL_CFG1_CAL_IN_OFF_MASK

#define PWMV2_CAL_CFG1_CAL_IN_OFF_MASK   (0x1FU)

◆ PWMV2_CAL_CFG1_CAL_IN_OFF_SET

#define PWMV2_CAL_CFG1_CAL_IN_OFF_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK)

◆ PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT

#define PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT   (0U)

◆ PWMV2_CAL_CFG1_CAL_LIM_LO_GET

#define PWMV2_CAL_CFG1_CAL_LIM_LO_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT)

◆ PWMV2_CAL_CFG1_CAL_LIM_LO_MASK

#define PWMV2_CAL_CFG1_CAL_LIM_LO_MASK   (0x1F00U)

◆ PWMV2_CAL_CFG1_CAL_LIM_LO_SET

#define PWMV2_CAL_CFG1_CAL_LIM_LO_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK)

◆ PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT

#define PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT   (8U)

◆ PWMV2_CAL_CFG1_CAL_LIM_UP_GET

#define PWMV2_CAL_CFG1_CAL_LIM_UP_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT)

◆ PWMV2_CAL_CFG1_CAL_LIM_UP_MASK

#define PWMV2_CAL_CFG1_CAL_LIM_UP_MASK   (0x1F0000UL)

◆ PWMV2_CAL_CFG1_CAL_LIM_UP_SET

#define PWMV2_CAL_CFG1_CAL_LIM_UP_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK)

◆ PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT

#define PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT   (16U)

◆ PWMV2_CAL_CFG1_CAL_LL_EN_GET

#define PWMV2_CAL_CFG1_CAL_LL_EN_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT)

◆ PWMV2_CAL_CFG1_CAL_LL_EN_MASK

#define PWMV2_CAL_CFG1_CAL_LL_EN_MASK   (0x8000U)

◆ PWMV2_CAL_CFG1_CAL_LL_EN_SET

#define PWMV2_CAL_CFG1_CAL_LL_EN_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK)

◆ PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT

#define PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT   (15U)

◆ PWMV2_CAL_CFG1_CAL_LU_EN_GET

#define PWMV2_CAL_CFG1_CAL_LU_EN_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT)

◆ PWMV2_CAL_CFG1_CAL_LU_EN_MASK

#define PWMV2_CAL_CFG1_CAL_LU_EN_MASK   (0x800000UL)

◆ PWMV2_CAL_CFG1_CAL_LU_EN_SET

#define PWMV2_CAL_CFG1_CAL_LU_EN_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK)

◆ PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT

#define PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT   (23U)

◆ PWMV2_CAL_CFG1_CAL_T_INDEX_GET

#define PWMV2_CAL_CFG1_CAL_T_INDEX_GET (   x)    (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT)

◆ PWMV2_CAL_CFG1_CAL_T_INDEX_MASK

#define PWMV2_CAL_CFG1_CAL_T_INDEX_MASK   (0x30000000UL)

◆ PWMV2_CAL_CFG1_CAL_T_INDEX_SET

#define PWMV2_CAL_CFG1_CAL_T_INDEX_SET (   x)    (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK)

◆ PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT

#define PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT   (28U)

◆ PWMV2_CAPTURE_NEG_0

#define PWMV2_CAPTURE_NEG_0   (0UL)

◆ PWMV2_CAPTURE_NEG_1

#define PWMV2_CAPTURE_NEG_1   (1UL)

◆ PWMV2_CAPTURE_NEG_2

#define PWMV2_CAPTURE_NEG_2   (2UL)

◆ PWMV2_CAPTURE_NEG_3

#define PWMV2_CAPTURE_NEG_3   (3UL)

◆ PWMV2_CAPTURE_NEG_4

#define PWMV2_CAPTURE_NEG_4   (4UL)

◆ PWMV2_CAPTURE_NEG_5

#define PWMV2_CAPTURE_NEG_5   (5UL)

◆ PWMV2_CAPTURE_NEG_6

#define PWMV2_CAPTURE_NEG_6   (6UL)

◆ PWMV2_CAPTURE_NEG_7

#define PWMV2_CAPTURE_NEG_7   (7UL)

◆ PWMV2_CAPTURE_NEG_CAPTURE_NEG_GET

#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_GET (   x)    (((uint32_t)(x) & PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK) >> PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT)

◆ PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK

#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK   (0xFFFFFF00UL)

◆ PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT

#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT   (8U)

◆ PWMV2_CAPTURE_POS_0

#define PWMV2_CAPTURE_POS_0   (0UL)

◆ PWMV2_CAPTURE_POS_1

#define PWMV2_CAPTURE_POS_1   (1UL)

◆ PWMV2_CAPTURE_POS_2

#define PWMV2_CAPTURE_POS_2   (2UL)

◆ PWMV2_CAPTURE_POS_3

#define PWMV2_CAPTURE_POS_3   (3UL)

◆ PWMV2_CAPTURE_POS_4

#define PWMV2_CAPTURE_POS_4   (4UL)

◆ PWMV2_CAPTURE_POS_5

#define PWMV2_CAPTURE_POS_5   (5UL)

◆ PWMV2_CAPTURE_POS_6

#define PWMV2_CAPTURE_POS_6   (6UL)

◆ PWMV2_CAPTURE_POS_7

#define PWMV2_CAPTURE_POS_7   (7UL)

◆ PWMV2_CAPTURE_POS_CAPTURE_POS_GET

#define PWMV2_CAPTURE_POS_CAPTURE_POS_GET (   x)    (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_POS_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT)

◆ PWMV2_CAPTURE_POS_CAPTURE_POS_MASK

#define PWMV2_CAPTURE_POS_CAPTURE_POS_MASK   (0xFFFFFF00UL)

◆ PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT

#define PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT   (8U)

◆ PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_GET

#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_GET (   x)    (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT)

◆ PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK

#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK   (0x10U)

◆ PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SET

#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SET (   x)    (((uint32_t)(x) << PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK)

◆ PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT

#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT   (4U)

◆ PWMV2_CAPTURE_POS_CNT_INDEX_GET

#define PWMV2_CAPTURE_POS_CNT_INDEX_GET (   x)    (((uint32_t)(x) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK) >> PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT)

◆ PWMV2_CAPTURE_POS_CNT_INDEX_MASK

#define PWMV2_CAPTURE_POS_CNT_INDEX_MASK   (0x3U)

◆ PWMV2_CAPTURE_POS_CNT_INDEX_SET

#define PWMV2_CAPTURE_POS_CNT_INDEX_SET (   x)    (((uint32_t)(x) << PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK)

◆ PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT

#define PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT   (0U)

◆ PWMV2_CMP_0

#define PWMV2_CMP_0   (0UL)

◆ PWMV2_CMP_1

#define PWMV2_CMP_1   (1UL)

◆ PWMV2_CMP_10

#define PWMV2_CMP_10   (10UL)

◆ PWMV2_CMP_11

#define PWMV2_CMP_11   (11UL)

◆ PWMV2_CMP_12

#define PWMV2_CMP_12   (12UL)

◆ PWMV2_CMP_13

#define PWMV2_CMP_13   (13UL)

◆ PWMV2_CMP_14

#define PWMV2_CMP_14   (14UL)

◆ PWMV2_CMP_15

#define PWMV2_CMP_15   (15UL)

◆ PWMV2_CMP_16

#define PWMV2_CMP_16   (16UL)

◆ PWMV2_CMP_17

#define PWMV2_CMP_17   (17UL)

◆ PWMV2_CMP_18

#define PWMV2_CMP_18   (18UL)

◆ PWMV2_CMP_19

#define PWMV2_CMP_19   (19UL)

◆ PWMV2_CMP_2

#define PWMV2_CMP_2   (2UL)

◆ PWMV2_CMP_20

#define PWMV2_CMP_20   (20UL)

◆ PWMV2_CMP_21

#define PWMV2_CMP_21   (21UL)

◆ PWMV2_CMP_22

#define PWMV2_CMP_22   (22UL)

◆ PWMV2_CMP_23

#define PWMV2_CMP_23   (23UL)

◆ PWMV2_CMP_3

#define PWMV2_CMP_3   (3UL)

◆ PWMV2_CMP_4

#define PWMV2_CMP_4   (4UL)

◆ PWMV2_CMP_5

#define PWMV2_CMP_5   (5UL)

◆ PWMV2_CMP_6

#define PWMV2_CMP_6   (6UL)

◆ PWMV2_CMP_7

#define PWMV2_CMP_7   (7UL)

◆ PWMV2_CMP_8

#define PWMV2_CMP_8   (8UL)

◆ PWMV2_CMP_9

#define PWMV2_CMP_9   (9UL)

◆ PWMV2_CMP_CFG_CMP_CNT_GET

#define PWMV2_CMP_CFG_CMP_CNT_GET (   x)    (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_CNT_MASK) >> PWMV2_CMP_CFG_CMP_CNT_SHIFT)

◆ PWMV2_CMP_CFG_CMP_CNT_MASK

#define PWMV2_CMP_CFG_CMP_CNT_MASK   (0xC000U)

◆ PWMV2_CMP_CFG_CMP_CNT_SET

#define PWMV2_CMP_CFG_CMP_CNT_SET (   x)    (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_CNT_SHIFT) & PWMV2_CMP_CFG_CMP_CNT_MASK)

◆ PWMV2_CMP_CFG_CMP_CNT_SHIFT

#define PWMV2_CMP_CFG_CMP_CNT_SHIFT   (14U)

◆ PWMV2_CMP_CFG_CMP_IN_SEL_GET

#define PWMV2_CMP_CFG_CMP_IN_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK) >> PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT)

◆ PWMV2_CMP_CFG_CMP_IN_SEL_MASK

#define PWMV2_CMP_CFG_CMP_IN_SEL_MASK   (0x3F0000UL)

◆ PWMV2_CMP_CFG_CMP_IN_SEL_SET

#define PWMV2_CMP_CFG_CMP_IN_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK)

◆ PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT

#define PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT   (16U)

◆ PWMV2_CMP_CFG_CMP_TRIG_SEL_GET

#define PWMV2_CMP_CFG_CMP_TRIG_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK) >> PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT)

◆ PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK

#define PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK   (0x70000000UL)

◆ PWMV2_CMP_CFG_CMP_TRIG_SEL_SET

#define PWMV2_CMP_CFG_CMP_TRIG_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK)

◆ PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT

#define PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT   (28U)

◆ PWMV2_CMP_CFG_CMP_UPDATE_TIME_GET

#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_GET (   x)    (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK) >> PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT)

◆ PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK

#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK   (0x7000000UL)

◆ PWMV2_CMP_CFG_CMP_UPDATE_TIME_SET

#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SET (   x)    (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK)

◆ PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT

#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT   (24U)

◆ PWMV2_CMP_VAL_WORK_0

#define PWMV2_CMP_VAL_WORK_0   (0UL)

◆ PWMV2_CMP_VAL_WORK_1

#define PWMV2_CMP_VAL_WORK_1   (1UL)

◆ PWMV2_CMP_VAL_WORK_10

#define PWMV2_CMP_VAL_WORK_10   (10UL)

◆ PWMV2_CMP_VAL_WORK_11

#define PWMV2_CMP_VAL_WORK_11   (11UL)

◆ PWMV2_CMP_VAL_WORK_12

#define PWMV2_CMP_VAL_WORK_12   (12UL)

◆ PWMV2_CMP_VAL_WORK_13

#define PWMV2_CMP_VAL_WORK_13   (13UL)

◆ PWMV2_CMP_VAL_WORK_14

#define PWMV2_CMP_VAL_WORK_14   (14UL)

◆ PWMV2_CMP_VAL_WORK_15

#define PWMV2_CMP_VAL_WORK_15   (15UL)

◆ PWMV2_CMP_VAL_WORK_16

#define PWMV2_CMP_VAL_WORK_16   (16UL)

◆ PWMV2_CMP_VAL_WORK_17

#define PWMV2_CMP_VAL_WORK_17   (17UL)

◆ PWMV2_CMP_VAL_WORK_18

#define PWMV2_CMP_VAL_WORK_18   (18UL)

◆ PWMV2_CMP_VAL_WORK_19

#define PWMV2_CMP_VAL_WORK_19   (19UL)

◆ PWMV2_CMP_VAL_WORK_2

#define PWMV2_CMP_VAL_WORK_2   (2UL)

◆ PWMV2_CMP_VAL_WORK_20

#define PWMV2_CMP_VAL_WORK_20   (20UL)

◆ PWMV2_CMP_VAL_WORK_21

#define PWMV2_CMP_VAL_WORK_21   (21UL)

◆ PWMV2_CMP_VAL_WORK_22

#define PWMV2_CMP_VAL_WORK_22   (22UL)

◆ PWMV2_CMP_VAL_WORK_23

#define PWMV2_CMP_VAL_WORK_23   (23UL)

◆ PWMV2_CMP_VAL_WORK_3

#define PWMV2_CMP_VAL_WORK_3   (3UL)

◆ PWMV2_CMP_VAL_WORK_4

#define PWMV2_CMP_VAL_WORK_4   (4UL)

◆ PWMV2_CMP_VAL_WORK_5

#define PWMV2_CMP_VAL_WORK_5   (5UL)

◆ PWMV2_CMP_VAL_WORK_6

#define PWMV2_CMP_VAL_WORK_6   (6UL)

◆ PWMV2_CMP_VAL_WORK_7

#define PWMV2_CMP_VAL_WORK_7   (7UL)

◆ PWMV2_CMP_VAL_WORK_8

#define PWMV2_CMP_VAL_WORK_8   (8UL)

◆ PWMV2_CMP_VAL_WORK_9

#define PWMV2_CMP_VAL_WORK_9   (9UL)

◆ PWMV2_CMP_VAL_WORK_VALUE_GET

#define PWMV2_CMP_VAL_WORK_VALUE_GET (   x)    (((uint32_t)(x) & PWMV2_CMP_VAL_WORK_VALUE_MASK) >> PWMV2_CMP_VAL_WORK_VALUE_SHIFT)

◆ PWMV2_CMP_VAL_WORK_VALUE_MASK

#define PWMV2_CMP_VAL_WORK_VALUE_MASK   (0xFFFFFFFFUL)

◆ PWMV2_CMP_VAL_WORK_VALUE_SHIFT

#define PWMV2_CMP_VAL_WORK_VALUE_SHIFT   (0U)

◆ PWMV2_CNT_0

#define PWMV2_CNT_0   (0UL)

◆ PWMV2_CNT_1

#define PWMV2_CNT_1   (1UL)

◆ PWMV2_CNT_2

#define PWMV2_CNT_2   (2UL)

◆ PWMV2_CNT_3

#define PWMV2_CNT_3   (3UL)

◆ PWMV2_CNT_CFG0_CNT_D_PARAM_GET

#define PWMV2_CNT_CFG0_CNT_D_PARAM_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK) >> PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT)

◆ PWMV2_CNT_CFG0_CNT_D_PARAM_MASK

#define PWMV2_CNT_CFG0_CNT_D_PARAM_MASK   (0x1FU)

◆ PWMV2_CNT_CFG0_CNT_D_PARAM_SET

#define PWMV2_CNT_CFG0_CNT_D_PARAM_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK)

◆ PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT

#define PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT   (0U)

◆ PWMV2_CNT_CFG0_RLD_CMP_SEL0_GET

#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT)

◆ PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK

#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK   (0x1F0000UL)

◆ PWMV2_CNT_CFG0_RLD_CMP_SEL0_SET

#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK)

◆ PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT

#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT   (16U)

◆ PWMV2_CNT_CFG0_RLD_CMP_SEL1_GET

#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT)

◆ PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK

#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK   (0x1F000000UL)

◆ PWMV2_CNT_CFG0_RLD_CMP_SEL1_SET

#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK)

◆ PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT

#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT   (24U)

◆ PWMV2_CNT_CFG0_RLD_TRIG_SEL_GET

#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK) >> PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT)

◆ PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK

#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK   (0x7000U)

◆ PWMV2_CNT_CFG0_RLD_TRIG_SEL_SET

#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK)

◆ PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT

#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT   (12U)

◆ PWMV2_CNT_CFG0_RLD_UPDATE_TIME_GET

#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK) >> PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT)

◆ PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK

#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK   (0x300U)

◆ PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SET

#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK)

◆ PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT

#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT   (8U)

◆ PWMV2_CNT_CFG1_CNT_DAC_INDEX_GET

#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK) >> PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT)

◆ PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK

#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK   (0x3000000UL)

◆ PWMV2_CNT_CFG1_CNT_DAC_INDEX_SET

#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK)

◆ PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT

#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT   (24U)

◆ PWMV2_CNT_CFG1_CNT_IN_OFF_GET

#define PWMV2_CNT_CFG1_CNT_IN_OFF_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK) >> PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT)

◆ PWMV2_CNT_CFG1_CNT_IN_OFF_MASK

#define PWMV2_CNT_CFG1_CNT_IN_OFF_MASK   (0x1FU)

◆ PWMV2_CNT_CFG1_CNT_IN_OFF_SET

#define PWMV2_CNT_CFG1_CNT_IN_OFF_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK)

◆ PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT

#define PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT   (0U)

◆ PWMV2_CNT_CFG1_CNT_LIM_LO_GET

#define PWMV2_CNT_CFG1_CNT_LIM_LO_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT)

◆ PWMV2_CNT_CFG1_CNT_LIM_LO_MASK

#define PWMV2_CNT_CFG1_CNT_LIM_LO_MASK   (0x1F00U)

◆ PWMV2_CNT_CFG1_CNT_LIM_LO_SET

#define PWMV2_CNT_CFG1_CNT_LIM_LO_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK)

◆ PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT

#define PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT   (8U)

◆ PWMV2_CNT_CFG1_CNT_LIM_UP_GET

#define PWMV2_CNT_CFG1_CNT_LIM_UP_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT)

◆ PWMV2_CNT_CFG1_CNT_LIM_UP_MASK

#define PWMV2_CNT_CFG1_CNT_LIM_UP_MASK   (0x1F0000UL)

◆ PWMV2_CNT_CFG1_CNT_LIM_UP_SET

#define PWMV2_CNT_CFG1_CNT_LIM_UP_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK)

◆ PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT

#define PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT   (16U)

◆ PWMV2_CNT_CFG1_CNT_LL_EN_GET

#define PWMV2_CNT_CFG1_CNT_LL_EN_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT)

◆ PWMV2_CNT_CFG1_CNT_LL_EN_MASK

#define PWMV2_CNT_CFG1_CNT_LL_EN_MASK   (0x8000U)

◆ PWMV2_CNT_CFG1_CNT_LL_EN_SET

#define PWMV2_CNT_CFG1_CNT_LL_EN_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK)

◆ PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT

#define PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT   (15U)

◆ PWMV2_CNT_CFG1_CNT_LU_EN_GET

#define PWMV2_CNT_CFG1_CNT_LU_EN_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT)

◆ PWMV2_CNT_CFG1_CNT_LU_EN_MASK

#define PWMV2_CNT_CFG1_CNT_LU_EN_MASK   (0x800000UL)

◆ PWMV2_CNT_CFG1_CNT_LU_EN_SET

#define PWMV2_CNT_CFG1_CNT_LU_EN_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK)

◆ PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT

#define PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT   (23U)

◆ PWMV2_CNT_CFG2_CNT_RELOAD_EN_GET

#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT)

◆ PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK

#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK   (0x80000000UL)

◆ PWMV2_CNT_CFG2_CNT_RELOAD_EN_SET

#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK)

◆ PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT

#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT   (31U)

◆ PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_GET

#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT)

◆ PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK

#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK   (0x7000000UL)

◆ PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SET

#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK)

◆ PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT

#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT   (24U)

◆ PWMV2_CNT_CFG2_CNT_TRIG0_GET

#define PWMV2_CNT_CFG2_CNT_TRIG0_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT)

◆ PWMV2_CNT_CFG2_CNT_TRIG0_MASK

#define PWMV2_CNT_CFG2_CNT_TRIG0_MASK   (0xFU)

◆ PWMV2_CNT_CFG2_CNT_TRIG0_SET

#define PWMV2_CNT_CFG2_CNT_TRIG0_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK)

◆ PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT

#define PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT   (0U)

◆ PWMV2_CNT_CFG2_CNT_TRIG1_GET

#define PWMV2_CNT_CFG2_CNT_TRIG1_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT)

◆ PWMV2_CNT_CFG2_CNT_TRIG1_MASK

#define PWMV2_CNT_CFG2_CNT_TRIG1_MASK   (0xF000U)

◆ PWMV2_CNT_CFG2_CNT_TRIG1_SET

#define PWMV2_CNT_CFG2_CNT_TRIG1_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK)

◆ PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT

#define PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT   (12U)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_EN0_GET

#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK

#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK   (0x80U)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SET

#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT

#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT   (7U)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_EN1_GET

#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK

#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK   (0x80000UL)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SET

#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT

#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT   (19U)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_GET

#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK

#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK   (0x700U)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SET

#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT

#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT   (8U)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_GET

#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK

#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK   (0x700000UL)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SET

#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK)

◆ PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT

#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT   (20U)

◆ PWMV2_CNT_CFG3_CNT_BURST_GET

#define PWMV2_CNT_CFG3_CNT_BURST_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_BURST_MASK) >> PWMV2_CNT_CFG3_CNT_BURST_SHIFT)

◆ PWMV2_CNT_CFG3_CNT_BURST_MASK

#define PWMV2_CNT_CFG3_CNT_BURST_MASK   (0xFFFFU)

◆ PWMV2_CNT_CFG3_CNT_BURST_SET

#define PWMV2_CNT_CFG3_CNT_BURST_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_BURST_SHIFT) & PWMV2_CNT_CFG3_CNT_BURST_MASK)

◆ PWMV2_CNT_CFG3_CNT_BURST_SHIFT

#define PWMV2_CNT_CFG3_CNT_BURST_SHIFT   (0U)

◆ PWMV2_CNT_CFG3_CNT_HW_START_EN_GET

#define PWMV2_CNT_CFG3_CNT_HW_START_EN_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK) >> PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT)

◆ PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK

#define PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK   (0x20000UL)

◆ PWMV2_CNT_CFG3_CNT_HW_START_EN_SET

#define PWMV2_CNT_CFG3_CNT_HW_START_EN_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK)

◆ PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT

#define PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT   (17U)

◆ PWMV2_CNT_CFG3_CNT_START_SEL_GET

#define PWMV2_CNT_CFG3_CNT_START_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK) >> PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT)

◆ PWMV2_CNT_CFG3_CNT_START_SEL_MASK

#define PWMV2_CNT_CFG3_CNT_START_SEL_MASK   (0x700000UL)

◆ PWMV2_CNT_CFG3_CNT_START_SEL_SET

#define PWMV2_CNT_CFG3_CNT_START_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK)

◆ PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT

#define PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT   (20U)

◆ PWMV2_CNT_GLBCFG_CNT_SW_START_GET

#define PWMV2_CNT_GLBCFG_CNT_SW_START_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK) >> PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT)

◆ PWMV2_CNT_GLBCFG_CNT_SW_START_MASK

#define PWMV2_CNT_GLBCFG_CNT_SW_START_MASK   (0xF0000UL)

◆ PWMV2_CNT_GLBCFG_CNT_SW_START_SET

#define PWMV2_CNT_GLBCFG_CNT_SW_START_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK)

◆ PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT

#define PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT   (16U)

◆ PWMV2_CNT_GLBCFG_TIMER_ENABLE_GET

#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK) >> PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT)

◆ PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK

#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK   (0xFU)

◆ PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET

#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK)

◆ PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT

#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT   (0U)

◆ PWMV2_CNT_GLBCFG_TIMER_RESET_GET

#define PWMV2_CNT_GLBCFG_TIMER_RESET_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK) >> PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT)

◆ PWMV2_CNT_GLBCFG_TIMER_RESET_MASK

#define PWMV2_CNT_GLBCFG_TIMER_RESET_MASK   (0xF00U)

◆ PWMV2_CNT_GLBCFG_TIMER_RESET_SET

#define PWMV2_CNT_GLBCFG_TIMER_RESET_SET (   x)    (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK)

◆ PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT

#define PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT   (8U)

◆ PWMV2_CNT_RELOAD_WORK_0

#define PWMV2_CNT_RELOAD_WORK_0   (0UL)

◆ PWMV2_CNT_RELOAD_WORK_1

#define PWMV2_CNT_RELOAD_WORK_1   (1UL)

◆ PWMV2_CNT_RELOAD_WORK_2

#define PWMV2_CNT_RELOAD_WORK_2   (2UL)

◆ PWMV2_CNT_RELOAD_WORK_3

#define PWMV2_CNT_RELOAD_WORK_3   (3UL)

◆ PWMV2_CNT_RELOAD_WORK_VALUE_GET

#define PWMV2_CNT_RELOAD_WORK_VALUE_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_RELOAD_WORK_VALUE_MASK) >> PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT)

◆ PWMV2_CNT_RELOAD_WORK_VALUE_MASK

#define PWMV2_CNT_RELOAD_WORK_VALUE_MASK   (0xFFFFFFFFUL)

◆ PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT

#define PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT   (0U)

◆ PWMV2_CNT_VAL_0

#define PWMV2_CNT_VAL_0   (0UL)

◆ PWMV2_CNT_VAL_1

#define PWMV2_CNT_VAL_1   (1UL)

◆ PWMV2_CNT_VAL_2

#define PWMV2_CNT_VAL_2   (2UL)

◆ PWMV2_CNT_VAL_3

#define PWMV2_CNT_VAL_3   (3UL)

◆ PWMV2_CNT_VAL_VALUE_GET

#define PWMV2_CNT_VAL_VALUE_GET (   x)    (((uint32_t)(x) & PWMV2_CNT_VAL_VALUE_MASK) >> PWMV2_CNT_VAL_VALUE_SHIFT)

◆ PWMV2_CNT_VAL_VALUE_MASK

#define PWMV2_CNT_VAL_VALUE_MASK   (0xFFFFFFFFUL)

◆ PWMV2_CNT_VAL_VALUE_SHIFT

#define PWMV2_CNT_VAL_VALUE_SHIFT   (0U)

◆ PWMV2_DAC_VALUE_SV_0

#define PWMV2_DAC_VALUE_SV_0   (0UL)

◆ PWMV2_DAC_VALUE_SV_1

#define PWMV2_DAC_VALUE_SV_1   (1UL)

◆ PWMV2_DAC_VALUE_SV_2

#define PWMV2_DAC_VALUE_SV_2   (2UL)

◆ PWMV2_DAC_VALUE_SV_3

#define PWMV2_DAC_VALUE_SV_3   (3UL)

◆ PWMV2_DAC_VALUE_SV_VALUE_GET

#define PWMV2_DAC_VALUE_SV_VALUE_GET (   x)    (((uint32_t)(x) & PWMV2_DAC_VALUE_SV_VALUE_MASK) >> PWMV2_DAC_VALUE_SV_VALUE_SHIFT)

◆ PWMV2_DAC_VALUE_SV_VALUE_MASK

#define PWMV2_DAC_VALUE_SV_VALUE_MASK   (0xFFFFFFFFUL)

◆ PWMV2_DAC_VALUE_SV_VALUE_SET

#define PWMV2_DAC_VALUE_SV_VALUE_SET (   x)    (((uint32_t)(x) << PWMV2_DAC_VALUE_SV_VALUE_SHIFT) & PWMV2_DAC_VALUE_SV_VALUE_MASK)

◆ PWMV2_DAC_VALUE_SV_VALUE_SHIFT

#define PWMV2_DAC_VALUE_SV_VALUE_SHIFT   (0U)

◆ PWMV2_DMA_EN_DMA0_EN_GET

#define PWMV2_DMA_EN_DMA0_EN_GET (   x)    (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_EN_MASK) >> PWMV2_DMA_EN_DMA0_EN_SHIFT)

◆ PWMV2_DMA_EN_DMA0_EN_MASK

#define PWMV2_DMA_EN_DMA0_EN_MASK   (0x80U)

◆ PWMV2_DMA_EN_DMA0_EN_SET

#define PWMV2_DMA_EN_DMA0_EN_SET (   x)    (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_EN_SHIFT) & PWMV2_DMA_EN_DMA0_EN_MASK)

◆ PWMV2_DMA_EN_DMA0_EN_SHIFT

#define PWMV2_DMA_EN_DMA0_EN_SHIFT   (7U)

◆ PWMV2_DMA_EN_DMA0_SEL_GET

#define PWMV2_DMA_EN_DMA0_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_SEL_MASK) >> PWMV2_DMA_EN_DMA0_SEL_SHIFT)

◆ PWMV2_DMA_EN_DMA0_SEL_MASK

#define PWMV2_DMA_EN_DMA0_SEL_MASK   (0x1FU)

◆ PWMV2_DMA_EN_DMA0_SEL_SET

#define PWMV2_DMA_EN_DMA0_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_SEL_SHIFT) & PWMV2_DMA_EN_DMA0_SEL_MASK)

◆ PWMV2_DMA_EN_DMA0_SEL_SHIFT

#define PWMV2_DMA_EN_DMA0_SEL_SHIFT   (0U)

◆ PWMV2_DMA_EN_DMA1_EN_GET

#define PWMV2_DMA_EN_DMA1_EN_GET (   x)    (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_EN_MASK) >> PWMV2_DMA_EN_DMA1_EN_SHIFT)

◆ PWMV2_DMA_EN_DMA1_EN_MASK

#define PWMV2_DMA_EN_DMA1_EN_MASK   (0x8000U)

◆ PWMV2_DMA_EN_DMA1_EN_SET

#define PWMV2_DMA_EN_DMA1_EN_SET (   x)    (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_EN_SHIFT) & PWMV2_DMA_EN_DMA1_EN_MASK)

◆ PWMV2_DMA_EN_DMA1_EN_SHIFT

#define PWMV2_DMA_EN_DMA1_EN_SHIFT   (15U)

◆ PWMV2_DMA_EN_DMA1_SEL_GET

#define PWMV2_DMA_EN_DMA1_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_SEL_MASK) >> PWMV2_DMA_EN_DMA1_SEL_SHIFT)

◆ PWMV2_DMA_EN_DMA1_SEL_MASK

#define PWMV2_DMA_EN_DMA1_SEL_MASK   (0x1F00U)

◆ PWMV2_DMA_EN_DMA1_SEL_SET

#define PWMV2_DMA_EN_DMA1_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_SEL_SHIFT) & PWMV2_DMA_EN_DMA1_SEL_MASK)

◆ PWMV2_DMA_EN_DMA1_SEL_SHIFT

#define PWMV2_DMA_EN_DMA1_SEL_SHIFT   (8U)

◆ PWMV2_DMA_EN_DMA2_EN_GET

#define PWMV2_DMA_EN_DMA2_EN_GET (   x)    (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_EN_MASK) >> PWMV2_DMA_EN_DMA2_EN_SHIFT)

◆ PWMV2_DMA_EN_DMA2_EN_MASK

#define PWMV2_DMA_EN_DMA2_EN_MASK   (0x800000UL)

◆ PWMV2_DMA_EN_DMA2_EN_SET

#define PWMV2_DMA_EN_DMA2_EN_SET (   x)    (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_EN_SHIFT) & PWMV2_DMA_EN_DMA2_EN_MASK)

◆ PWMV2_DMA_EN_DMA2_EN_SHIFT

#define PWMV2_DMA_EN_DMA2_EN_SHIFT   (23U)

◆ PWMV2_DMA_EN_DMA2_SEL_GET

#define PWMV2_DMA_EN_DMA2_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_SEL_MASK) >> PWMV2_DMA_EN_DMA2_SEL_SHIFT)

◆ PWMV2_DMA_EN_DMA2_SEL_MASK

#define PWMV2_DMA_EN_DMA2_SEL_MASK   (0x1F0000UL)

◆ PWMV2_DMA_EN_DMA2_SEL_SET

#define PWMV2_DMA_EN_DMA2_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_SEL_SHIFT) & PWMV2_DMA_EN_DMA2_SEL_MASK)

◆ PWMV2_DMA_EN_DMA2_SEL_SHIFT

#define PWMV2_DMA_EN_DMA2_SEL_SHIFT   (16U)

◆ PWMV2_DMA_EN_DMA3_EN_GET

#define PWMV2_DMA_EN_DMA3_EN_GET (   x)    (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_EN_MASK) >> PWMV2_DMA_EN_DMA3_EN_SHIFT)

◆ PWMV2_DMA_EN_DMA3_EN_MASK

#define PWMV2_DMA_EN_DMA3_EN_MASK   (0x80000000UL)

◆ PWMV2_DMA_EN_DMA3_EN_SET

#define PWMV2_DMA_EN_DMA3_EN_SET (   x)    (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_EN_SHIFT) & PWMV2_DMA_EN_DMA3_EN_MASK)

◆ PWMV2_DMA_EN_DMA3_EN_SHIFT

#define PWMV2_DMA_EN_DMA3_EN_SHIFT   (31U)

◆ PWMV2_DMA_EN_DMA3_SEL_GET

#define PWMV2_DMA_EN_DMA3_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_SEL_MASK) >> PWMV2_DMA_EN_DMA3_SEL_SHIFT)

◆ PWMV2_DMA_EN_DMA3_SEL_MASK

#define PWMV2_DMA_EN_DMA3_SEL_MASK   (0x1F000000UL)

◆ PWMV2_DMA_EN_DMA3_SEL_SET

#define PWMV2_DMA_EN_DMA3_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_SEL_SHIFT) & PWMV2_DMA_EN_DMA3_SEL_MASK)

◆ PWMV2_DMA_EN_DMA3_SEL_SHIFT

#define PWMV2_DMA_EN_DMA3_SEL_SHIFT   (24U)

◆ PWMV2_FORCE_MODE_FORCE_MODE_GET

#define PWMV2_FORCE_MODE_FORCE_MODE_GET (   x)    (((uint32_t)(x) & PWMV2_FORCE_MODE_FORCE_MODE_MASK) >> PWMV2_FORCE_MODE_FORCE_MODE_SHIFT)

◆ PWMV2_FORCE_MODE_FORCE_MODE_MASK

#define PWMV2_FORCE_MODE_FORCE_MODE_MASK   (0xFFFFU)

◆ PWMV2_FORCE_MODE_FORCE_MODE_SET

#define PWMV2_FORCE_MODE_FORCE_MODE_SET (   x)    (((uint32_t)(x) << PWMV2_FORCE_MODE_FORCE_MODE_SHIFT) & PWMV2_FORCE_MODE_FORCE_MODE_MASK)

◆ PWMV2_FORCE_MODE_FORCE_MODE_SHIFT

#define PWMV2_FORCE_MODE_FORCE_MODE_SHIFT   (0U)

◆ PWMV2_FORCE_MODE_POLARITY_GET

#define PWMV2_FORCE_MODE_POLARITY_GET (   x)    (((uint32_t)(x) & PWMV2_FORCE_MODE_POLARITY_MASK) >> PWMV2_FORCE_MODE_POLARITY_SHIFT)

◆ PWMV2_FORCE_MODE_POLARITY_MASK

#define PWMV2_FORCE_MODE_POLARITY_MASK   (0xFF0000UL)

◆ PWMV2_FORCE_MODE_POLARITY_SET

#define PWMV2_FORCE_MODE_POLARITY_SET (   x)    (((uint32_t)(x) << PWMV2_FORCE_MODE_POLARITY_SHIFT) & PWMV2_FORCE_MODE_POLARITY_MASK)

◆ PWMV2_FORCE_MODE_POLARITY_SHIFT

#define PWMV2_FORCE_MODE_POLARITY_SHIFT   (16U)

◆ PWMV2_FORCE_WORK_FORCE_MODE_GET

#define PWMV2_FORCE_WORK_FORCE_MODE_GET (   x)    (((uint32_t)(x) & PWMV2_FORCE_WORK_FORCE_MODE_MASK) >> PWMV2_FORCE_WORK_FORCE_MODE_SHIFT)

◆ PWMV2_FORCE_WORK_FORCE_MODE_MASK

#define PWMV2_FORCE_WORK_FORCE_MODE_MASK   (0xFFFFU)

◆ PWMV2_FORCE_WORK_FORCE_MODE_SHIFT

#define PWMV2_FORCE_WORK_FORCE_MODE_SHIFT   (0U)

◆ PWMV2_FORCE_WORK_OUT_POLARITY_GET

#define PWMV2_FORCE_WORK_OUT_POLARITY_GET (   x)    (((uint32_t)(x) & PWMV2_FORCE_WORK_OUT_POLARITY_MASK) >> PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT)

◆ PWMV2_FORCE_WORK_OUT_POLARITY_MASK

#define PWMV2_FORCE_WORK_OUT_POLARITY_MASK   (0xFF0000UL)

◆ PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT

#define PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT   (16U)

◆ PWMV2_GLB_CTRL2_DAC_SW_MODE_GET

#define PWMV2_GLB_CTRL2_DAC_SW_MODE_GET (   x)    (((uint32_t)(x) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK) >> PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT)

◆ PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK

#define PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK   (0xF000000UL)

◆ PWMV2_GLB_CTRL2_DAC_SW_MODE_SET

#define PWMV2_GLB_CTRL2_DAC_SW_MODE_SET (   x)    (((uint32_t)(x) << PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK)

◆ PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT

#define PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT   (24U)

◆ PWMV2_GLB_CTRL2_DEBUG_IN_EN_GET

#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_GET (   x)    (((uint32_t)(x) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK) >> PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT)

◆ PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK

#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK   (0x200000UL)

◆ PWMV2_GLB_CTRL2_DEBUG_IN_EN_SET

#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SET (   x)    (((uint32_t)(x) << PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK)

◆ PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT

#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT   (21U)

◆ PWMV2_GLB_CTRL2_FAULT_CLEAR_GET

#define PWMV2_GLB_CTRL2_FAULT_CLEAR_GET (   x)    (((uint32_t)(x) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK) >> PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT)

◆ PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK

#define PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK   (0xFF00U)

◆ PWMV2_GLB_CTRL2_FAULT_CLEAR_SET

#define PWMV2_GLB_CTRL2_FAULT_CLEAR_SET (   x)    (((uint32_t)(x) << PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK)

◆ PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT

#define PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT   (8U)

◆ PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_GET

#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_GET (   x)    (((uint32_t)(x) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK) >> PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT)

◆ PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK

#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK   (0x1U)

◆ PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SET

#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SET (   x)    (((uint32_t)(x) << PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK)

◆ PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT

#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT   (0U)

◆ PWMV2_GLB_CTRL_FRAC_DISABLE_GET

#define PWMV2_GLB_CTRL_FRAC_DISABLE_GET (   x)    (((uint32_t)(x) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK) >> PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT)

◆ PWMV2_GLB_CTRL_FRAC_DISABLE_MASK

#define PWMV2_GLB_CTRL_FRAC_DISABLE_MASK   (0x8U)

◆ PWMV2_GLB_CTRL_FRAC_DISABLE_SET

#define PWMV2_GLB_CTRL_FRAC_DISABLE_SET (   x)    (((uint32_t)(x) << PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK)

◆ PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT

#define PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT   (3U)

◆ PWMV2_GLB_CTRL_HR_PWM_EN_GET

#define PWMV2_GLB_CTRL_HR_PWM_EN_GET (   x)    (((uint32_t)(x) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK) >> PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT)

◆ PWMV2_GLB_CTRL_HR_PWM_EN_MASK

#define PWMV2_GLB_CTRL_HR_PWM_EN_MASK   (0x10U)

◆ PWMV2_GLB_CTRL_HR_PWM_EN_SET

#define PWMV2_GLB_CTRL_HR_PWM_EN_SET (   x)    (((uint32_t)(x) << PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK)

◆ PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT

#define PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT   (4U)

◆ PWMV2_GLB_CTRL_OUTPUT_DELAY_GET

#define PWMV2_GLB_CTRL_OUTPUT_DELAY_GET (   x)    (((uint32_t)(x) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK) >> PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT)

◆ PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK

#define PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK   (0x300U)

◆ PWMV2_GLB_CTRL_OUTPUT_DELAY_SET

#define PWMV2_GLB_CTRL_OUTPUT_DELAY_SET (   x)    (((uint32_t)(x) << PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK)

◆ PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT

#define PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT   (8U)

◆ PWMV2_GLB_CTRL_SW_FORCE_GET

#define PWMV2_GLB_CTRL_SW_FORCE_GET (   x)    (((uint32_t)(x) & PWMV2_GLB_CTRL_SW_FORCE_MASK) >> PWMV2_GLB_CTRL_SW_FORCE_SHIFT)

◆ PWMV2_GLB_CTRL_SW_FORCE_MASK

#define PWMV2_GLB_CTRL_SW_FORCE_MASK   (0xFF0000UL)

◆ PWMV2_GLB_CTRL_SW_FORCE_SET

#define PWMV2_GLB_CTRL_SW_FORCE_SET (   x)    (((uint32_t)(x) << PWMV2_GLB_CTRL_SW_FORCE_SHIFT) & PWMV2_GLB_CTRL_SW_FORCE_MASK)

◆ PWMV2_GLB_CTRL_SW_FORCE_SHIFT

#define PWMV2_GLB_CTRL_SW_FORCE_SHIFT   (16U)

◆ PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_GET

#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK) >> PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT)

◆ PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK

#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK   (0xFU)

◆ PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SET

#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK)

◆ PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT

#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT   (0U)

◆ PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_GET

#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK) >> PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT)

◆ PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK

#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK   (0xFFU)

◆ PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SET

#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK)

◆ PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT

#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT   (0U)

◆ PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_GET

#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK) >> PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT)

◆ PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK

#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK   (0xFFU)

◆ PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SET

#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK)

◆ PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT

#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT   (0U)

◆ PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_GET

#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK) >> PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT)

◆ PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK

#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK   (0xFFFFFFUL)

◆ PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SET

#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK)

◆ PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT

#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT   (0U)

◆ PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_GET

#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK) >> PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT)

◆ PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK

#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK   (0xFFU)

◆ PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET

#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK)

◆ PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT

#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT   (0U)

◆ PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_GET

#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK) >> PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT)

◆ PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK

#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK   (0x80000000UL)

◆ PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SET

#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK)

◆ PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT

#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT   (31U)

◆ PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_GET

#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK) >> PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT)

◆ PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK

#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK   (0xFU)

◆ PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SET

#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK)

◆ PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT

#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT   (0U)

◆ PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_GET

#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK) >> PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT)

◆ PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK

#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK   (0xFU)

◆ PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SET

#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK)

◆ PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT

#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT   (0U)

◆ PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_GET

#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK) >> PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT)

◆ PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK

#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK   (0xFFU)

◆ PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SET

#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK)

◆ PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT

#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT   (0U)

◆ PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_GET

#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK) >> PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT)

◆ PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK

#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK   (0xFFU)

◆ PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SET

#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK)

◆ PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT

#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT   (0U)

◆ PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_GET

#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK) >> PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT)

◆ PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK

#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK   (0xFFFFFFUL)

◆ PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SET

#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK)

◆ PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT

#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT   (0U)

◆ PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_GET

#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK) >> PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT)

◆ PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK

#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK   (0xFFU)

◆ PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SET

#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK)

◆ PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT

#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT   (0U)

◆ PWMV2_IRQ_STS_IRQ_BURSTEND_GET

#define PWMV2_IRQ_STS_IRQ_BURSTEND_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_BURSTEND_MASK) >> PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT)

◆ PWMV2_IRQ_STS_IRQ_BURSTEND_MASK

#define PWMV2_IRQ_STS_IRQ_BURSTEND_MASK   (0x20U)

◆ PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT

#define PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT   (5U)

◆ PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_GET

#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK) >> PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT)

◆ PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK

#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK   (0x80000000UL)

◆ PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SET

#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK)

◆ PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT

#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT   (31U)

◆ PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_GET

#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT)

◆ PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK

#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK   (0x8U)

◆ PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT

#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT   (3U)

◆ PWMV2_IRQ_STS_IRQ_CAPTURE_POS_GET

#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT)

◆ PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK

#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK   (0x4U)

◆ PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT

#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT   (2U)

◆ PWMV2_IRQ_STS_IRQ_CMP_GET

#define PWMV2_IRQ_STS_IRQ_CMP_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CMP_MASK) >> PWMV2_IRQ_STS_IRQ_CMP_SHIFT)

◆ PWMV2_IRQ_STS_IRQ_CMP_MASK

#define PWMV2_IRQ_STS_IRQ_CMP_MASK   (0x1U)

◆ PWMV2_IRQ_STS_IRQ_CMP_SHIFT

#define PWMV2_IRQ_STS_IRQ_CMP_SHIFT   (0U)

◆ PWMV2_IRQ_STS_IRQ_FAULT_GET

#define PWMV2_IRQ_STS_IRQ_FAULT_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_FAULT_MASK) >> PWMV2_IRQ_STS_IRQ_FAULT_SHIFT)

◆ PWMV2_IRQ_STS_IRQ_FAULT_MASK

#define PWMV2_IRQ_STS_IRQ_FAULT_MASK   (0x10U)

◆ PWMV2_IRQ_STS_IRQ_FAULT_SHIFT

#define PWMV2_IRQ_STS_IRQ_FAULT_SHIFT   (4U)

◆ PWMV2_IRQ_STS_IRQ_RELOAD_GET

#define PWMV2_IRQ_STS_IRQ_RELOAD_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_RELOAD_MASK) >> PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT)

◆ PWMV2_IRQ_STS_IRQ_RELOAD_MASK

#define PWMV2_IRQ_STS_IRQ_RELOAD_MASK   (0x2U)

◆ PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT

#define PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT   (1U)

◆ PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_GET

#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_GET (   x)    (((uint32_t)(x) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK) >> PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT)

◆ PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK

#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK   (0xFU)

◆ PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SET

#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SET (   x)    (((uint32_t)(x) << PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK)

◆ PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT

#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT   (0U)

◆ PWMV2_PWM_0

#define PWMV2_PWM_0   (0UL)

◆ PWMV2_PWM_1

#define PWMV2_PWM_1   (1UL)

◆ PWMV2_PWM_2

#define PWMV2_PWM_2   (2UL)

◆ PWMV2_PWM_3

#define PWMV2_PWM_3   (3UL)

◆ PWMV2_PWM_4

#define PWMV2_PWM_4   (4UL)

◆ PWMV2_PWM_5

#define PWMV2_PWM_5   (5UL)

◆ PWMV2_PWM_6

#define PWMV2_PWM_6   (6UL)

◆ PWMV2_PWM_7

#define PWMV2_PWM_7   (7UL)

◆ PWMV2_PWM_CFG0_FAULT_EN_ASYNC_GET

#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT)

◆ PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK

#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK   (0x20U)

◆ PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SET

#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK)

◆ PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT

#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT   (5U)

◆ PWMV2_PWM_CFG0_FAULT_EN_SYNC_GET

#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT)

◆ PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK

#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK   (0x10U)

◆ PWMV2_PWM_CFG0_FAULT_EN_SYNC_SET

#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK)

◆ PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT

#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT   (4U)

◆ PWMV2_PWM_CFG0_FAULT_POL_ASYNC_GET

#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT)

◆ PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK

#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK   (0x40U)

◆ PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SET

#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK)

◆ PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT

#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT   (6U)

◆ PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_GET

#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT)

◆ PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK

#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK   (0xF00U)

◆ PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SET

#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK)

◆ PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT

#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT   (8U)

◆ PWMV2_PWM_CFG0_OUT_POLARITY_GET

#define PWMV2_PWM_CFG0_OUT_POLARITY_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK) >> PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT)

◆ PWMV2_PWM_CFG0_OUT_POLARITY_MASK

#define PWMV2_PWM_CFG0_OUT_POLARITY_MASK   (0x2U)

◆ PWMV2_PWM_CFG0_OUT_POLARITY_SET

#define PWMV2_PWM_CFG0_OUT_POLARITY_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK)

◆ PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT

#define PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT   (1U)

◆ PWMV2_PWM_CFG0_POL_UPDATE_SEL_GET

#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK) >> PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT)

◆ PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK

#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK   (0x4U)

◆ PWMV2_PWM_CFG0_POL_UPDATE_SEL_SET

#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK)

◆ PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT

#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT   (2U)

◆ PWMV2_PWM_CFG0_POLARITY_OPT0_GET

#define PWMV2_PWM_CFG0_POLARITY_OPT0_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK) >> PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT)

◆ PWMV2_PWM_CFG0_POLARITY_OPT0_MASK

#define PWMV2_PWM_CFG0_POLARITY_OPT0_MASK   (0x1U)

◆ PWMV2_PWM_CFG0_POLARITY_OPT0_SET

#define PWMV2_PWM_CFG0_POLARITY_OPT0_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK)

◆ PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT

#define PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT   (0U)

◆ PWMV2_PWM_CFG0_TRIG_SEL4_GET

#define PWMV2_PWM_CFG0_TRIG_SEL4_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK) >> PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT)

◆ PWMV2_PWM_CFG0_TRIG_SEL4_MASK

#define PWMV2_PWM_CFG0_TRIG_SEL4_MASK   (0x1000000UL)

◆ PWMV2_PWM_CFG0_TRIG_SEL4_SET

#define PWMV2_PWM_CFG0_TRIG_SEL4_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK)

◆ PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT

#define PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT   (24U)

◆ PWMV2_PWM_CFG1_FAULT_MODE_GET

#define PWMV2_PWM_CFG1_FAULT_MODE_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_MODE_MASK) >> PWMV2_PWM_CFG1_FAULT_MODE_SHIFT)

◆ PWMV2_PWM_CFG1_FAULT_MODE_MASK

#define PWMV2_PWM_CFG1_FAULT_MODE_MASK   (0x3000000UL)

◆ PWMV2_PWM_CFG1_FAULT_MODE_SET

#define PWMV2_PWM_CFG1_FAULT_MODE_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_MODE_SHIFT) & PWMV2_PWM_CFG1_FAULT_MODE_MASK)

◆ PWMV2_PWM_CFG1_FAULT_MODE_SHIFT

#define PWMV2_PWM_CFG1_FAULT_MODE_SHIFT   (24U)

◆ PWMV2_PWM_CFG1_FAULT_REC_SEL_GET

#define PWMV2_PWM_CFG1_FAULT_REC_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT)

◆ PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK

#define PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK   (0x7U)

◆ PWMV2_PWM_CFG1_FAULT_REC_SEL_SET

#define PWMV2_PWM_CFG1_FAULT_REC_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK)

◆ PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT

#define PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT   (0U)

◆ PWMV2_PWM_CFG1_FAULT_REC_TIME_GET

#define PWMV2_PWM_CFG1_FAULT_REC_TIME_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT)

◆ PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK

#define PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK   (0xC00000UL)

◆ PWMV2_PWM_CFG1_FAULT_REC_TIME_SET

#define PWMV2_PWM_CFG1_FAULT_REC_TIME_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK)

◆ PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT

#define PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT   (22U)

◆ PWMV2_PWM_CFG1_FORCE_ACT_SEL_GET

#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT)

◆ PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK

#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK   (0x700U)

◆ PWMV2_PWM_CFG1_FORCE_ACT_SEL_SET

#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK)

◆ PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT

#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT   (8U)

◆ PWMV2_PWM_CFG1_FORCE_TIME_GET

#define PWMV2_PWM_CFG1_FORCE_TIME_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_TIME_SHIFT)

◆ PWMV2_PWM_CFG1_FORCE_TIME_MASK

#define PWMV2_PWM_CFG1_FORCE_TIME_MASK   (0x30000UL)

◆ PWMV2_PWM_CFG1_FORCE_TIME_SET

#define PWMV2_PWM_CFG1_FORCE_TIME_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_TIME_MASK)

◆ PWMV2_PWM_CFG1_FORCE_TIME_SHIFT

#define PWMV2_PWM_CFG1_FORCE_TIME_SHIFT   (16U)

◆ PWMV2_PWM_CFG1_FORCE_TRIG_SEL_GET

#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT)

◆ PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK

#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK   (0x7000U)

◆ PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SET

#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK)

◆ PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT

#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT   (12U)

◆ PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_GET

#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT)

◆ PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK

#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK   (0xC000000UL)

◆ PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SET

#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK)

◆ PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT

#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT   (26U)

◆ PWMV2_PWM_CFG1_HIGHZ_EN_N_GET

#define PWMV2_PWM_CFG1_HIGHZ_EN_N_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK) >> PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT)

◆ PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK

#define PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK   (0x10000000UL)

◆ PWMV2_PWM_CFG1_HIGHZ_EN_N_SET

#define PWMV2_PWM_CFG1_HIGHZ_EN_N_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK)

◆ PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT

#define PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT   (28U)

◆ PWMV2_PWM_CFG1_PAIR_MODE_GET

#define PWMV2_PWM_CFG1_PAIR_MODE_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_PAIR_MODE_MASK) >> PWMV2_PWM_CFG1_PAIR_MODE_SHIFT)

◆ PWMV2_PWM_CFG1_PAIR_MODE_MASK

#define PWMV2_PWM_CFG1_PAIR_MODE_MASK   (0x100000UL)

◆ PWMV2_PWM_CFG1_PAIR_MODE_SET

#define PWMV2_PWM_CFG1_PAIR_MODE_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_PAIR_MODE_SHIFT) & PWMV2_PWM_CFG1_PAIR_MODE_MASK)

◆ PWMV2_PWM_CFG1_PAIR_MODE_SHIFT

#define PWMV2_PWM_CFG1_PAIR_MODE_SHIFT   (20U)

◆ PWMV2_PWM_CFG1_PWM_FORCE_SEL_GET

#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK) >> PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT)

◆ PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK

#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK   (0x70U)

◆ PWMV2_PWM_CFG1_PWM_FORCE_SEL_SET

#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK)

◆ PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT

#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT   (4U)

◆ PWMV2_PWM_CFG1_PWM_LOGIC_GET

#define PWMV2_PWM_CFG1_PWM_LOGIC_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK) >> PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT)

◆ PWMV2_PWM_CFG1_PWM_LOGIC_MASK

#define PWMV2_PWM_CFG1_PWM_LOGIC_MASK   (0xC0000UL)

◆ PWMV2_PWM_CFG1_PWM_LOGIC_SET

#define PWMV2_PWM_CFG1_PWM_LOGIC_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK)

◆ PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT

#define PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT   (18U)

◆ PWMV2_PWM_CFG1_SW_FORCE_EN_GET

#define PWMV2_PWM_CFG1_SW_FORCE_EN_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK) >> PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT)

◆ PWMV2_PWM_CFG1_SW_FORCE_EN_MASK

#define PWMV2_PWM_CFG1_SW_FORCE_EN_MASK   (0x200000UL)

◆ PWMV2_PWM_CFG1_SW_FORCE_EN_SET

#define PWMV2_PWM_CFG1_SW_FORCE_EN_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK)

◆ PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT

#define PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT   (21U)

◆ PWMV2_PWM_DEAD_AREA_DEAD_AREA_GET

#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_GET (   x)    (((uint32_t)(x) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK) >> PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT)

◆ PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK

#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK   (0xFFFFFFUL)

◆ PWMV2_PWM_DEAD_AREA_DEAD_AREA_SET

#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SET (   x)    (((uint32_t)(x) << PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK)

◆ PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT

#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT   (0U)

◆ PWMV2_SHADOW_VAL_0

#define PWMV2_SHADOW_VAL_0   (0UL)

◆ PWMV2_SHADOW_VAL_1

#define PWMV2_SHADOW_VAL_1   (1UL)

◆ PWMV2_SHADOW_VAL_10

#define PWMV2_SHADOW_VAL_10   (10UL)

◆ PWMV2_SHADOW_VAL_11

#define PWMV2_SHADOW_VAL_11   (11UL)

◆ PWMV2_SHADOW_VAL_12

#define PWMV2_SHADOW_VAL_12   (12UL)

◆ PWMV2_SHADOW_VAL_13

#define PWMV2_SHADOW_VAL_13   (13UL)

◆ PWMV2_SHADOW_VAL_14

#define PWMV2_SHADOW_VAL_14   (14UL)

◆ PWMV2_SHADOW_VAL_15

#define PWMV2_SHADOW_VAL_15   (15UL)

◆ PWMV2_SHADOW_VAL_16

#define PWMV2_SHADOW_VAL_16   (16UL)

◆ PWMV2_SHADOW_VAL_17

#define PWMV2_SHADOW_VAL_17   (17UL)

◆ PWMV2_SHADOW_VAL_18

#define PWMV2_SHADOW_VAL_18   (18UL)

◆ PWMV2_SHADOW_VAL_19

#define PWMV2_SHADOW_VAL_19   (19UL)

◆ PWMV2_SHADOW_VAL_2

#define PWMV2_SHADOW_VAL_2   (2UL)

◆ PWMV2_SHADOW_VAL_20

#define PWMV2_SHADOW_VAL_20   (20UL)

◆ PWMV2_SHADOW_VAL_21

#define PWMV2_SHADOW_VAL_21   (21UL)

◆ PWMV2_SHADOW_VAL_22

#define PWMV2_SHADOW_VAL_22   (22UL)

◆ PWMV2_SHADOW_VAL_23

#define PWMV2_SHADOW_VAL_23   (23UL)

◆ PWMV2_SHADOW_VAL_24

#define PWMV2_SHADOW_VAL_24   (24UL)

◆ PWMV2_SHADOW_VAL_25

#define PWMV2_SHADOW_VAL_25   (25UL)

◆ PWMV2_SHADOW_VAL_26

#define PWMV2_SHADOW_VAL_26   (26UL)

◆ PWMV2_SHADOW_VAL_27

#define PWMV2_SHADOW_VAL_27   (27UL)

◆ PWMV2_SHADOW_VAL_3

#define PWMV2_SHADOW_VAL_3   (3UL)

◆ PWMV2_SHADOW_VAL_4

#define PWMV2_SHADOW_VAL_4   (4UL)

◆ PWMV2_SHADOW_VAL_5

#define PWMV2_SHADOW_VAL_5   (5UL)

◆ PWMV2_SHADOW_VAL_6

#define PWMV2_SHADOW_VAL_6   (6UL)

◆ PWMV2_SHADOW_VAL_7

#define PWMV2_SHADOW_VAL_7   (7UL)

◆ PWMV2_SHADOW_VAL_8

#define PWMV2_SHADOW_VAL_8   (8UL)

◆ PWMV2_SHADOW_VAL_9

#define PWMV2_SHADOW_VAL_9   (9UL)

◆ PWMV2_SHADOW_VAL_VALUE_GET

#define PWMV2_SHADOW_VAL_VALUE_GET (   x)    (((uint32_t)(x) & PWMV2_SHADOW_VAL_VALUE_MASK) >> PWMV2_SHADOW_VAL_VALUE_SHIFT)

◆ PWMV2_SHADOW_VAL_VALUE_MASK

#define PWMV2_SHADOW_VAL_VALUE_MASK   (0xFFFFFFFFUL)

◆ PWMV2_SHADOW_VAL_VALUE_SET

#define PWMV2_SHADOW_VAL_VALUE_SET (   x)    (((uint32_t)(x) << PWMV2_SHADOW_VAL_VALUE_SHIFT) & PWMV2_SHADOW_VAL_VALUE_MASK)

◆ PWMV2_SHADOW_VAL_VALUE_SHIFT

#define PWMV2_SHADOW_VAL_VALUE_SHIFT   (0U)

◆ PWMV2_TRIGGER_CFG_0

#define PWMV2_TRIGGER_CFG_0   (0UL)

◆ PWMV2_TRIGGER_CFG_1

#define PWMV2_TRIGGER_CFG_1   (1UL)

◆ PWMV2_TRIGGER_CFG_2

#define PWMV2_TRIGGER_CFG_2   (2UL)

◆ PWMV2_TRIGGER_CFG_3

#define PWMV2_TRIGGER_CFG_3   (3UL)

◆ PWMV2_TRIGGER_CFG_4

#define PWMV2_TRIGGER_CFG_4   (4UL)

◆ PWMV2_TRIGGER_CFG_5

#define PWMV2_TRIGGER_CFG_5   (5UL)

◆ PWMV2_TRIGGER_CFG_6

#define PWMV2_TRIGGER_CFG_6   (6UL)

◆ PWMV2_TRIGGER_CFG_7

#define PWMV2_TRIGGER_CFG_7   (7UL)

◆ PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_GET

#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_GET (   x)    (((uint32_t)(x) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK) >> PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT)

◆ PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK

#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK   (0x1FU)

◆ PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SET

#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SET (   x)    (((uint32_t)(x) << PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK)

◆ PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT

#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT   (0U)

◆ PWMV2_UNLOCK_UNLOCK_BIT_GET

#define PWMV2_UNLOCK_UNLOCK_BIT_GET (   x)    (((uint32_t)(x) & PWMV2_UNLOCK_UNLOCK_BIT_MASK) >> PWMV2_UNLOCK_UNLOCK_BIT_SHIFT)

◆ PWMV2_UNLOCK_UNLOCK_BIT_MASK

#define PWMV2_UNLOCK_UNLOCK_BIT_MASK   (0xFFFFFFFFUL)

◆ PWMV2_UNLOCK_UNLOCK_BIT_SET

#define PWMV2_UNLOCK_UNLOCK_BIT_SET (   x)    (((uint32_t)(x) << PWMV2_UNLOCK_UNLOCK_BIT_SHIFT) & PWMV2_UNLOCK_UNLOCK_BIT_MASK)

◆ PWMV2_UNLOCK_UNLOCK_BIT_SHIFT

#define PWMV2_UNLOCK_UNLOCK_BIT_SHIFT   (0U)

◆ PWMV2_WORK_CTRL0_SHADOW_UNLOCK_GET

#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_GET (   x)    (((uint32_t)(x) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK) >> PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT)

◆ PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK

#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK   (0x80000000UL)

◆ PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SET

#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SET (   x)    (((uint32_t)(x) << PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK)

◆ PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT

#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT   (31U)

◆ PWMV2_WORK_CTRL1_SHADOW_LOCK_GET

#define PWMV2_WORK_CTRL1_SHADOW_LOCK_GET (   x)    (((uint32_t)(x) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK) >> PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT)

◆ PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK

#define PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK   (0x80000000UL)

◆ PWMV2_WORK_CTRL1_SHADOW_LOCK_SET

#define PWMV2_WORK_CTRL1_SHADOW_LOCK_SET (   x)    (((uint32_t)(x) << PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK)

◆ PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT

#define PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT   (31U)