HPM SDK
HPMicro Software Development Kit
hpm_sdadc_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SDADC_H
10 #define HPM_SDADC_H
11 
12 typedef struct {
13  __RW uint32_t CTRL; /* 0x0: SDADC control register */
14  __RW uint32_t CLK_DIV; /* 0x4: clock divider */
15  __RW uint32_t TTB; /* 0x8: Total Transfer Bits */
16  __RW uint32_t START_OP; /* 0xC: Start_Of_Operation */
17  __RW uint32_t MISC; /* 0x10: Misc Control */
18  __R uint32_t ST; /* 0x14: Status Register */
19 } SDADC_Type;
20 
21 
22 /* Bitfield definition for register: CTRL */
23 /*
24  * SDM_CFG (RW)
25  *
26  * SDM analog part Configuration
27  */
28 #define SDADC_CTRL_SDM_CFG_MASK (0xFF00000UL)
29 #define SDADC_CTRL_SDM_CFG_SHIFT (20U)
30 #define SDADC_CTRL_SDM_CFG_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_CFG_SHIFT) & SDADC_CTRL_SDM_CFG_MASK)
31 #define SDADC_CTRL_SDM_CFG_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_CFG_MASK) >> SDADC_CTRL_SDM_CFG_SHIFT)
32 
33 /*
34  * SDM_PGA_CE_SEL (RW)
35  *
36  * SDM_PGA_CE_SEL
37  */
38 #define SDADC_CTRL_SDM_PGA_CE_SEL_MASK (0xC0000UL)
39 #define SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT (18U)
40 #define SDADC_CTRL_SDM_PGA_CE_SEL_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT) & SDADC_CTRL_SDM_PGA_CE_SEL_MASK)
41 #define SDADC_CTRL_SDM_PGA_CE_SEL_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_PGA_CE_SEL_MASK) >> SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT)
42 
43 /*
44  * SDM_PGA_CH_SEL (RW)
45  *
46  * SDM_PGA_CH_SEL
47  */
48 #define SDADC_CTRL_SDM_PGA_CH_SEL_MASK (0x3C000UL)
49 #define SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT (14U)
50 #define SDADC_CTRL_SDM_PGA_CH_SEL_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT) & SDADC_CTRL_SDM_PGA_CH_SEL_MASK)
51 #define SDADC_CTRL_SDM_PGA_CH_SEL_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_PGA_CH_SEL_MASK) >> SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT)
52 
53 /*
54  * CFG_CDS_CMD (RW)
55  *
56  * config the common mode voltage of CDS CAP
57  */
58 #define SDADC_CTRL_CFG_CDS_CMD_MASK (0x2000U)
59 #define SDADC_CTRL_CFG_CDS_CMD_SHIFT (13U)
60 #define SDADC_CTRL_CFG_CDS_CMD_SET(x) (((uint32_t)(x) << SDADC_CTRL_CFG_CDS_CMD_SHIFT) & SDADC_CTRL_CFG_CDS_CMD_MASK)
61 #define SDADC_CTRL_CFG_CDS_CMD_GET(x) (((uint32_t)(x) & SDADC_CTRL_CFG_CDS_CMD_MASK) >> SDADC_CTRL_CFG_CDS_CMD_SHIFT)
62 
63 /*
64  * LP_MODE_SDM (RW)
65  *
66  * lowpower mode of SDM
67  */
68 #define SDADC_CTRL_LP_MODE_SDM_MASK (0xE00U)
69 #define SDADC_CTRL_LP_MODE_SDM_SHIFT (9U)
70 #define SDADC_CTRL_LP_MODE_SDM_SET(x) (((uint32_t)(x) << SDADC_CTRL_LP_MODE_SDM_SHIFT) & SDADC_CTRL_LP_MODE_SDM_MASK)
71 #define SDADC_CTRL_LP_MODE_SDM_GET(x) (((uint32_t)(x) & SDADC_CTRL_LP_MODE_SDM_MASK) >> SDADC_CTRL_LP_MODE_SDM_SHIFT)
72 
73 /*
74  * LP_MODE_PGA (RW)
75  *
76  * lowpower mode of PGA
77  */
78 #define SDADC_CTRL_LP_MODE_PGA_MASK (0x1C0U)
79 #define SDADC_CTRL_LP_MODE_PGA_SHIFT (6U)
80 #define SDADC_CTRL_LP_MODE_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_LP_MODE_PGA_SHIFT) & SDADC_CTRL_LP_MODE_PGA_MASK)
81 #define SDADC_CTRL_LP_MODE_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_LP_MODE_PGA_MASK) >> SDADC_CTRL_LP_MODE_PGA_SHIFT)
82 
83 /*
84  * ANA_PWUP (RW)
85  *
86  * 1. Asserted to power up the analog part
87  * 0: Shut off the power for the analog part
88  */
89 #define SDADC_CTRL_ANA_PWUP_MASK (0x20U)
90 #define SDADC_CTRL_ANA_PWUP_SHIFT (5U)
91 #define SDADC_CTRL_ANA_PWUP_SET(x) (((uint32_t)(x) << SDADC_CTRL_ANA_PWUP_SHIFT) & SDADC_CTRL_ANA_PWUP_MASK)
92 #define SDADC_CTRL_ANA_PWUP_GET(x) (((uint32_t)(x) & SDADC_CTRL_ANA_PWUP_MASK) >> SDADC_CTRL_ANA_PWUP_SHIFT)
93 
94 /*
95  * BYPASS_PGA (RW)
96  *
97  * 1: PGA is bypassed
98  * 0: PGA is enabled
99  */
100 #define SDADC_CTRL_BYPASS_PGA_MASK (0x10U)
101 #define SDADC_CTRL_BYPASS_PGA_SHIFT (4U)
102 #define SDADC_CTRL_BYPASS_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_BYPASS_PGA_SHIFT) & SDADC_CTRL_BYPASS_PGA_MASK)
103 #define SDADC_CTRL_BYPASS_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_BYPASS_PGA_MASK) >> SDADC_CTRL_BYPASS_PGA_SHIFT)
104 
105 /*
106  * CONT_MODE (RW)
107  *
108  * 1: continuous mode of ADC conversion
109  * 0: burst mode of ADC conversion.
110  */
111 #define SDADC_CTRL_CONT_MODE_MASK (0x8U)
112 #define SDADC_CTRL_CONT_MODE_SHIFT (3U)
113 #define SDADC_CTRL_CONT_MODE_SET(x) (((uint32_t)(x) << SDADC_CTRL_CONT_MODE_SHIFT) & SDADC_CTRL_CONT_MODE_MASK)
114 #define SDADC_CTRL_CONT_MODE_GET(x) (((uint32_t)(x) & SDADC_CTRL_CONT_MODE_MASK) >> SDADC_CTRL_CONT_MODE_SHIFT)
115 
116 /*
117  * RST_SDM (RW)
118  *
119  * 1: reset SDM. Should be de-asserted by software
120  * 0: no reset SDM
121  */
122 #define SDADC_CTRL_RST_SDM_MASK (0x4U)
123 #define SDADC_CTRL_RST_SDM_SHIFT (2U)
124 #define SDADC_CTRL_RST_SDM_SET(x) (((uint32_t)(x) << SDADC_CTRL_RST_SDM_SHIFT) & SDADC_CTRL_RST_SDM_MASK)
125 #define SDADC_CTRL_RST_SDM_GET(x) (((uint32_t)(x) & SDADC_CTRL_RST_SDM_MASK) >> SDADC_CTRL_RST_SDM_SHIFT)
126 
127 /*
128  * RST_PGA (RW)
129  *
130  * 1: reset PGA. Should be de-asserted by software
131  * 0: no reset PGA
132  */
133 #define SDADC_CTRL_RST_PGA_MASK (0x2U)
134 #define SDADC_CTRL_RST_PGA_SHIFT (1U)
135 #define SDADC_CTRL_RST_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_RST_PGA_SHIFT) & SDADC_CTRL_RST_PGA_MASK)
136 #define SDADC_CTRL_RST_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_RST_PGA_MASK) >> SDADC_CTRL_RST_PGA_SHIFT)
137 
138 /*
139  * EN (RW)
140  *
141  * Module enable, to enable clok divder. Etc
142  */
143 #define SDADC_CTRL_EN_MASK (0x1U)
144 #define SDADC_CTRL_EN_SHIFT (0U)
145 #define SDADC_CTRL_EN_SET(x) (((uint32_t)(x) << SDADC_CTRL_EN_SHIFT) & SDADC_CTRL_EN_MASK)
146 #define SDADC_CTRL_EN_GET(x) (((uint32_t)(x) & SDADC_CTRL_EN_MASK) >> SDADC_CTRL_EN_SHIFT)
147 
148 /* Bitfield definition for register: CLK_DIV */
149 /*
150  * FACTOR (RW)
151  *
152  * 0: disable clock output
153  * 1: bypass the clock divider
154  * 2: divide the clock by 2
155  * …
156  * n: divide the clock by n
157  */
158 #define SDADC_CLK_DIV_FACTOR_MASK (0xFFU)
159 #define SDADC_CLK_DIV_FACTOR_SHIFT (0U)
160 #define SDADC_CLK_DIV_FACTOR_SET(x) (((uint32_t)(x) << SDADC_CLK_DIV_FACTOR_SHIFT) & SDADC_CLK_DIV_FACTOR_MASK)
161 #define SDADC_CLK_DIV_FACTOR_GET(x) (((uint32_t)(x) & SDADC_CLK_DIV_FACTOR_MASK) >> SDADC_CLK_DIV_FACTOR_SHIFT)
162 
163 /* Bitfield definition for register: TTB */
164 /*
165  * VAL (RW)
166  *
167  * the maximal number of output bits when ADC is in burst mode
168  */
169 #define SDADC_TTB_VAL_MASK (0xFFFFFUL)
170 #define SDADC_TTB_VAL_SHIFT (0U)
171 #define SDADC_TTB_VAL_SET(x) (((uint32_t)(x) << SDADC_TTB_VAL_SHIFT) & SDADC_TTB_VAL_MASK)
172 #define SDADC_TTB_VAL_GET(x) (((uint32_t)(x) & SDADC_TTB_VAL_MASK) >> SDADC_TTB_VAL_SHIFT)
173 
174 /* Bitfield definition for register: START_OP */
175 /*
176  * SDM_EN (RW)
177  *
178  * 1. Enable sigma-delta ADC. Auto clear in burst mode when TTB bits are received. In cont mode, must be cleared manually.
179  * 0: disable sigma-delta ADC
180  */
181 #define SDADC_START_OP_SDM_EN_MASK (0x1U)
182 #define SDADC_START_OP_SDM_EN_SHIFT (0U)
183 #define SDADC_START_OP_SDM_EN_SET(x) (((uint32_t)(x) << SDADC_START_OP_SDM_EN_SHIFT) & SDADC_START_OP_SDM_EN_MASK)
184 #define SDADC_START_OP_SDM_EN_GET(x) (((uint32_t)(x) & SDADC_START_OP_SDM_EN_MASK) >> SDADC_START_OP_SDM_EN_SHIFT)
185 
186 /* Bitfield definition for register: MISC */
187 /*
188  * BURST_DONE_IE (RW)
189  *
190  * Asserted to enable BURST_DONE event interrupt. Should not be asserted for continuous mode.
191  */
192 #define SDADC_MISC_BURST_DONE_IE_MASK (0x2U)
193 #define SDADC_MISC_BURST_DONE_IE_SHIFT (1U)
194 #define SDADC_MISC_BURST_DONE_IE_SET(x) (((uint32_t)(x) << SDADC_MISC_BURST_DONE_IE_SHIFT) & SDADC_MISC_BURST_DONE_IE_MASK)
195 #define SDADC_MISC_BURST_DONE_IE_GET(x) (((uint32_t)(x) & SDADC_MISC_BURST_DONE_IE_MASK) >> SDADC_MISC_BURST_DONE_IE_SHIFT)
196 
197 /*
198  * PDM_CLK_SEL (RW)
199  *
200  * Asserted to use PDM clk input. Default to use MCLK which is directly from PLL.
201  */
202 #define SDADC_MISC_PDM_CLK_SEL_MASK (0x1U)
203 #define SDADC_MISC_PDM_CLK_SEL_SHIFT (0U)
204 #define SDADC_MISC_PDM_CLK_SEL_SET(x) (((uint32_t)(x) << SDADC_MISC_PDM_CLK_SEL_SHIFT) & SDADC_MISC_PDM_CLK_SEL_MASK)
205 #define SDADC_MISC_PDM_CLK_SEL_GET(x) (((uint32_t)(x) & SDADC_MISC_PDM_CLK_SEL_MASK) >> SDADC_MISC_PDM_CLK_SEL_SHIFT)
206 
207 /* Bitfield definition for register: ST */
208 /*
209  * ANA_RST (RO)
210  *
211  * Asserted when analog module is in reset mode.
212  */
213 #define SDADC_ST_ANA_RST_MASK (0x4U)
214 #define SDADC_ST_ANA_RST_SHIFT (2U)
215 #define SDADC_ST_ANA_RST_GET(x) (((uint32_t)(x) & SDADC_ST_ANA_RST_MASK) >> SDADC_ST_ANA_RST_SHIFT)
216 
217 /*
218  * DIV_STABLE (RO)
219  *
220  * Asserted when CLK_DIV reaches stable status. Cleared automatically when CLK_DIV[FACTOR] is assigned a different value.
221  */
222 #define SDADC_ST_DIV_STABLE_MASK (0x2U)
223 #define SDADC_ST_DIV_STABLE_SHIFT (1U)
224 #define SDADC_ST_DIV_STABLE_GET(x) (((uint32_t)(x) & SDADC_ST_DIV_STABLE_MASK) >> SDADC_ST_DIV_STABLE_SHIFT)
225 
226 /*
227  * BURST_DONE (RO)
228  *
229  * Asserted when burst transfer is done. Auto cleared after the ST register is read while this bit is asserted.
230  */
231 #define SDADC_ST_BURST_DONE_MASK (0x1U)
232 #define SDADC_ST_BURST_DONE_SHIFT (0U)
233 #define SDADC_ST_BURST_DONE_GET(x) (((uint32_t)(x) & SDADC_ST_BURST_DONE_MASK) >> SDADC_ST_BURST_DONE_SHIFT)
234 
235 
236 
237 
238 #endif /* HPM_SDADC_H */
SDADC_Type
Definition: hpm_sdadc_regs.h:12