 |
HPM SDK
HPMicro Software Development Kit
|
|
HPM SDK
HPMicro Software Development Kit
|
Go to the source code of this file.
Data Structures | |
| struct | VSC_Type |
| #define VSC_ABC_MODE_ENABLE_VSC_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_ENABLE_VSC_MASK) >> VSC_ABC_MODE_ENABLE_VSC_SHIFT) |
| #define VSC_ABC_MODE_ENABLE_VSC_MASK (0x8U) |
| #define VSC_ABC_MODE_ENABLE_VSC_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_ENABLE_VSC_SHIFT) & VSC_ABC_MODE_ENABLE_VSC_MASK) |
| #define VSC_ABC_MODE_ENABLE_VSC_SHIFT (3U) |
| #define VSC_ABC_MODE_PHASE_ABSENT_MODE_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK) >> VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT) |
| #define VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK (0x80000000UL) |
| #define VSC_ABC_MODE_PHASE_ABSENT_MODE_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT) & VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK) |
| #define VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT (31U) |
| #define VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_MASK) >> VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_SHIFT) |
| #define VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_MASK (0x40000000UL) |
| #define VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_SHIFT) & VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_MASK) |
| #define VSC_ABC_MODE_POSTION_USE_LAST_LOCKED_SHIFT (30U) |
| #define VSC_ABC_MODE_VALUE_A_LOC_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_VALUE_A_LOC_MASK) >> VSC_ABC_MODE_VALUE_A_LOC_SHIFT) |
| #define VSC_ABC_MODE_VALUE_A_LOC_MASK (0x30U) |
| #define VSC_ABC_MODE_VALUE_A_LOC_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_VALUE_A_LOC_SHIFT) & VSC_ABC_MODE_VALUE_A_LOC_MASK) |
| #define VSC_ABC_MODE_VALUE_A_LOC_SHIFT (4U) |
| #define VSC_ABC_MODE_VALUE_A_WIDTH_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_VALUE_A_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT) |
| #define VSC_ABC_MODE_VALUE_A_WIDTH_MASK (0xF0000UL) |
| #define VSC_ABC_MODE_VALUE_A_WIDTH_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_A_WIDTH_MASK) |
| #define VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT (16U) |
| #define VSC_ABC_MODE_VALUE_B_LOC_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_VALUE_B_LOC_MASK) >> VSC_ABC_MODE_VALUE_B_LOC_SHIFT) |
| #define VSC_ABC_MODE_VALUE_B_LOC_MASK (0x300U) |
| #define VSC_ABC_MODE_VALUE_B_LOC_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_VALUE_B_LOC_SHIFT) & VSC_ABC_MODE_VALUE_B_LOC_MASK) |
| #define VSC_ABC_MODE_VALUE_B_LOC_SHIFT (8U) |
| #define VSC_ABC_MODE_VALUE_B_WIDTH_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_VALUE_B_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT) |
| #define VSC_ABC_MODE_VALUE_B_WIDTH_MASK (0xF00000UL) |
| #define VSC_ABC_MODE_VALUE_B_WIDTH_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_B_WIDTH_MASK) |
| #define VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT (20U) |
| #define VSC_ABC_MODE_VALUE_C_LOC_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_VALUE_C_LOC_MASK) >> VSC_ABC_MODE_VALUE_C_LOC_SHIFT) |
| #define VSC_ABC_MODE_VALUE_C_LOC_MASK (0x3000U) |
| #define VSC_ABC_MODE_VALUE_C_LOC_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_VALUE_C_LOC_SHIFT) & VSC_ABC_MODE_VALUE_C_LOC_MASK) |
| #define VSC_ABC_MODE_VALUE_C_LOC_SHIFT (12U) |
| #define VSC_ABC_MODE_VALUE_C_WIDTH_GET | ( | x | ) | (((uint32_t)(x) & VSC_ABC_MODE_VALUE_C_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT) |
| #define VSC_ABC_MODE_VALUE_C_WIDTH_MASK (0xF000000UL) |
| #define VSC_ABC_MODE_VALUE_C_WIDTH_SET | ( | x | ) | (((uint32_t)(x) << VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_C_WIDTH_MASK) |
| #define VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT (24U) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_GET | ( | x | ) | (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK (0x1FU) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SET | ( | x | ) | (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT (0U) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_GET | ( | x | ) | (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK (0x1F00U) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SET | ( | x | ) | (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT (8U) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_GET | ( | x | ) | (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK (0x1F0000UL) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SET | ( | x | ) | (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK) |
| #define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT (16U) |
| #define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_GET | ( | x | ) | (((uint32_t)(x) & VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK) >> VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT) |
| #define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK (0xFFFFFFFFUL) |
| #define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SET | ( | x | ) | (((uint32_t)(x) << VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT) & VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK) |
| #define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT (0U) |
| #define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_GET | ( | x | ) | (((uint32_t)(x) & VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK) >> VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT) |
| #define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK (0xFFFFFFFFUL) |
| #define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SET | ( | x | ) | (((uint32_t)(x) << VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT) & VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK) |
| #define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT (0U) |
| #define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_GET | ( | x | ) | (((uint32_t)(x) & VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_MASK) >> VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_SHIFT) |
| #define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_MASK (0xFFFFFFFFUL) |
| #define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_SHIFT (0U) |
| #define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_GET | ( | x | ) | (((uint32_t)(x) & VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_MASK) >> VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_SHIFT) |
| #define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_MASK (0xFFFFFFFFUL) |
| #define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_SHIFT (0U) |
| #define VSC_BETA_NEGEDGE_BETA_NEGEDGE_GET | ( | x | ) | (((uint32_t)(x) & VSC_BETA_NEGEDGE_BETA_NEGEDGE_MASK) >> VSC_BETA_NEGEDGE_BETA_NEGEDGE_SHIFT) |
| #define VSC_BETA_NEGEDGE_BETA_NEGEDGE_MASK (0xFFFFFFFFUL) |
| #define VSC_BETA_NEGEDGE_BETA_NEGEDGE_SHIFT (0U) |
| #define VSC_BETA_POSEDGE_BETA_POSEDGE_GET | ( | x | ) | (((uint32_t)(x) & VSC_BETA_POSEDGE_BETA_POSEDGE_MASK) >> VSC_BETA_POSEDGE_BETA_POSEDGE_SHIFT) |
| #define VSC_BETA_POSEDGE_BETA_POSEDGE_MASK (0xFFFFFFFFUL) |
| #define VSC_BETA_POSEDGE_BETA_POSEDGE_SHIFT (0U) |
| #define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_GET | ( | x | ) | (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_A_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_A_COUNTER_SHIFT) |
| #define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_MASK (0xF00U) |
| #define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_SHIFT (8U) |
| #define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_GET | ( | x | ) | (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_B_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_B_COUNTER_SHIFT) |
| #define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_MASK (0xF0U) |
| #define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_SHIFT (4U) |
| #define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_GET | ( | x | ) | (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_C_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_C_COUNTER_SHIFT) |
| #define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_MASK (0xFU) |
| #define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_SHIFT (0U) |
| #define VSC_ID_NEGEDGE_ID_NEGEDGE_GET | ( | x | ) | (((uint32_t)(x) & VSC_ID_NEGEDGE_ID_NEGEDGE_MASK) >> VSC_ID_NEGEDGE_ID_NEGEDGE_SHIFT) |
| #define VSC_ID_NEGEDGE_ID_NEGEDGE_MASK (0xFFFFFFFFUL) |
| #define VSC_ID_NEGEDGE_ID_NEGEDGE_SHIFT (0U) |
| #define VSC_ID_POSEDGE_ID_POSEDGE_GET | ( | x | ) | (((uint32_t)(x) & VSC_ID_POSEDGE_ID_POSEDGE_MASK) >> VSC_ID_POSEDGE_ID_POSEDGE_SHIFT) |
| #define VSC_ID_POSEDGE_ID_POSEDGE_MASK (0xFFFFFFFFUL) |
| #define VSC_ID_POSEDGE_ID_POSEDGE_SHIFT (0U) |
| #define VSC_IQ_NEGEDGE_IQ_NEGEDGE_GET | ( | x | ) | (((uint32_t)(x) & VSC_IQ_NEGEDGE_IQ_NEGEDGE_MASK) >> VSC_IQ_NEGEDGE_IQ_NEGEDGE_SHIFT) |
| #define VSC_IQ_NEGEDGE_IQ_NEGEDGE_MASK (0xFFFFFFFFUL) |
| #define VSC_IQ_NEGEDGE_IQ_NEGEDGE_SHIFT (0U) |
| #define VSC_IQ_POSEDGE_IQ_POSEDGE_GET | ( | x | ) | (((uint32_t)(x) & VSC_IQ_POSEDGE_IQ_POSEDGE_MASK) >> VSC_IQ_POSEDGE_IQ_POSEDGE_SHIFT) |
| #define VSC_IQ_POSEDGE_IQ_POSEDGE_MASK (0xFFFFFFFFUL) |
| #define VSC_IQ_POSEDGE_IQ_POSEDGE_SHIFT (0U) |
| #define VSC_IRQ_ENABLE_IRQ_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & VSC_IRQ_ENABLE_IRQ_ENABLE_MASK) >> VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT) |
| #define VSC_IRQ_ENABLE_IRQ_ENABLE_MASK (0xFFFFFFFFUL) |
| #define VSC_IRQ_ENABLE_IRQ_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT) & VSC_IRQ_ENABLE_IRQ_ENABLE_MASK) |
| #define VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT (0U) |
| #define VSC_IRQ_STATUS_IRQ_STATUS_GET | ( | x | ) | (((uint32_t)(x) & VSC_IRQ_STATUS_IRQ_STATUS_MASK) >> VSC_IRQ_STATUS_IRQ_STATUS_SHIFT) |
| #define VSC_IRQ_STATUS_IRQ_STATUS_MASK (0xFFFFFFFFUL) |
| #define VSC_IRQ_STATUS_IRQ_STATUS_SET | ( | x | ) | (((uint32_t)(x) << VSC_IRQ_STATUS_IRQ_STATUS_SHIFT) & VSC_IRQ_STATUS_IRQ_STATUS_MASK) |
| #define VSC_IRQ_STATUS_IRQ_STATUS_SHIFT (0U) |
| #define VSC_POS_POLE_POS_POLE_GET | ( | x | ) | (((uint32_t)(x) & VSC_POS_POLE_POS_POLE_MASK) >> VSC_POS_POLE_POS_POLE_SHIFT) |
| #define VSC_POS_POLE_POS_POLE_MASK (0xFFFFU) |
| #define VSC_POS_POLE_POS_POLE_SET | ( | x | ) | (((uint32_t)(x) << VSC_POS_POLE_POS_POLE_SHIFT) & VSC_POS_POLE_POS_POLE_MASK) |
| #define VSC_POS_POLE_POS_POLE_SHIFT (0U) |
| #define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_GET | ( | x | ) | (((uint32_t)(x) & VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK) >> VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT) |
| #define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK (0xFFFFFFFFUL) |
| #define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SET | ( | x | ) | (((uint32_t)(x) << VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT) & VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK) |
| #define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT (0U) |
| #define VSC_POSITION_SW_POSITION_SW_GET | ( | x | ) | (((uint32_t)(x) & VSC_POSITION_SW_POSITION_SW_MASK) >> VSC_POSITION_SW_POSITION_SW_SHIFT) |
| #define VSC_POSITION_SW_POSITION_SW_MASK (0xFFFFFFFFUL) |
| #define VSC_POSITION_SW_POSITION_SW_SET | ( | x | ) | (((uint32_t)(x) << VSC_POSITION_SW_POSITION_SW_SHIFT) & VSC_POSITION_SW_POSITION_SW_MASK) |
| #define VSC_POSITION_SW_POSITION_SW_SHIFT (0U) |
| #define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_GET | ( | x | ) | (((uint32_t)(x) & VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK) >> VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT) |
| #define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK (0x30U) |
| #define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SET | ( | x | ) | (((uint32_t)(x) << VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT) & VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK) |
| #define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT (4U) |
| #define VSC_TIMELOCK_POSITION_CAPTURE_MODE_GET | ( | x | ) | (((uint32_t)(x) & VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK) >> VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT) |
| #define VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK (0x3000U) |
| #define VSC_TIMELOCK_POSITION_CAPTURE_MODE_SET | ( | x | ) | (((uint32_t)(x) << VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT) & VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK) |
| #define VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT (12U) |
| #define VSC_TIMELOCK_VALUE_COUNTER_SEL_GET | ( | x | ) | (((uint32_t)(x) & VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK) >> VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT) |
| #define VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK (0xFU) |
| #define VSC_TIMELOCK_VALUE_COUNTER_SEL_SET | ( | x | ) | (((uint32_t)(x) << VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT) & VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK) |
| #define VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT (0U) |
| #define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_GET | ( | x | ) | (((uint32_t)(x) & VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_MASK) >> VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_SHIFT) |
| #define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_MASK (0xFFFFFFFFUL) |
| #define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_SHIFT (0U) |
| #define VSC_TRIGGER_SW_TRIGGER_SW_GET | ( | x | ) | (((uint32_t)(x) & VSC_TRIGGER_SW_TRIGGER_SW_MASK) >> VSC_TRIGGER_SW_TRIGGER_SW_SHIFT) |
| #define VSC_TRIGGER_SW_TRIGGER_SW_MASK (0x1U) |
| #define VSC_TRIGGER_SW_TRIGGER_SW_SET | ( | x | ) | (((uint32_t)(x) << VSC_TRIGGER_SW_TRIGGER_SW_SHIFT) & VSC_TRIGGER_SW_TRIGGER_SW_MASK) |
| #define VSC_TRIGGER_SW_TRIGGER_SW_SHIFT (0U) |
| #define VSC_VALUE_A_DATA_OPT_OPT_0_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT) |
| #define VSC_VALUE_A_DATA_OPT_OPT_0_MASK (0xFU) |
| #define VSC_VALUE_A_DATA_OPT_OPT_0_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_0_MASK) |
| #define VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT (0U) |
| #define VSC_VALUE_A_DATA_OPT_OPT_1_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT) |
| #define VSC_VALUE_A_DATA_OPT_OPT_1_MASK (0xF0U) |
| #define VSC_VALUE_A_DATA_OPT_OPT_1_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_1_MASK) |
| #define VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT (4U) |
| #define VSC_VALUE_A_DATA_OPT_OPT_2_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT) |
| #define VSC_VALUE_A_DATA_OPT_OPT_2_MASK (0xF00U) |
| #define VSC_VALUE_A_DATA_OPT_OPT_2_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_2_MASK) |
| #define VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT (8U) |
| #define VSC_VALUE_A_DATA_OPT_OPT_3_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT) |
| #define VSC_VALUE_A_DATA_OPT_OPT_3_MASK (0xF000U) |
| #define VSC_VALUE_A_DATA_OPT_OPT_3_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_3_MASK) |
| #define VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT (12U) |
| #define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK) >> VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT) |
| #define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK (0xFFFFFFFFUL) |
| #define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT) & VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK) |
| #define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT (0U) |
| #define VSC_VALUE_A_SW_VALUE_A_SW_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_A_SW_VALUE_A_SW_MASK) >> VSC_VALUE_A_SW_VALUE_A_SW_SHIFT) |
| #define VSC_VALUE_A_SW_VALUE_A_SW_MASK (0xFFFFFFFFUL) |
| #define VSC_VALUE_A_SW_VALUE_A_SW_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_A_SW_VALUE_A_SW_SHIFT) & VSC_VALUE_A_SW_VALUE_A_SW_MASK) |
| #define VSC_VALUE_A_SW_VALUE_A_SW_SHIFT (0U) |
| #define VSC_VALUE_B_DATA_OPT_OPT_0_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT) |
| #define VSC_VALUE_B_DATA_OPT_OPT_0_MASK (0xFU) |
| #define VSC_VALUE_B_DATA_OPT_OPT_0_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_0_MASK) |
| #define VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT (0U) |
| #define VSC_VALUE_B_DATA_OPT_OPT_1_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT) |
| #define VSC_VALUE_B_DATA_OPT_OPT_1_MASK (0xF0U) |
| #define VSC_VALUE_B_DATA_OPT_OPT_1_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_1_MASK) |
| #define VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT (4U) |
| #define VSC_VALUE_B_DATA_OPT_OPT_2_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT) |
| #define VSC_VALUE_B_DATA_OPT_OPT_2_MASK (0xF00U) |
| #define VSC_VALUE_B_DATA_OPT_OPT_2_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_2_MASK) |
| #define VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT (8U) |
| #define VSC_VALUE_B_DATA_OPT_OPT_3_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT) |
| #define VSC_VALUE_B_DATA_OPT_OPT_3_MASK (0xF000U) |
| #define VSC_VALUE_B_DATA_OPT_OPT_3_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_3_MASK) |
| #define VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT (12U) |
| #define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK) >> VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT) |
| #define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK (0xFFFFFFFFUL) |
| #define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT) & VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK) |
| #define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT (0U) |
| #define VSC_VALUE_B_SW_VALUE_B_SW_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_B_SW_VALUE_B_SW_MASK) >> VSC_VALUE_B_SW_VALUE_B_SW_SHIFT) |
| #define VSC_VALUE_B_SW_VALUE_B_SW_MASK (0xFFFFFFFFUL) |
| #define VSC_VALUE_B_SW_VALUE_B_SW_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_B_SW_VALUE_B_SW_SHIFT) & VSC_VALUE_B_SW_VALUE_B_SW_MASK) |
| #define VSC_VALUE_B_SW_VALUE_B_SW_SHIFT (0U) |
| #define VSC_VALUE_C_DATA_OPT_OPT_0_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT) |
| #define VSC_VALUE_C_DATA_OPT_OPT_0_MASK (0xFU) |
| #define VSC_VALUE_C_DATA_OPT_OPT_0_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_0_MASK) |
| #define VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT (0U) |
| #define VSC_VALUE_C_DATA_OPT_OPT_1_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT) |
| #define VSC_VALUE_C_DATA_OPT_OPT_1_MASK (0xF0U) |
| #define VSC_VALUE_C_DATA_OPT_OPT_1_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_1_MASK) |
| #define VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT (4U) |
| #define VSC_VALUE_C_DATA_OPT_OPT_2_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT) |
| #define VSC_VALUE_C_DATA_OPT_OPT_2_MASK (0xF00U) |
| #define VSC_VALUE_C_DATA_OPT_OPT_2_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_2_MASK) |
| #define VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT (8U) |
| #define VSC_VALUE_C_DATA_OPT_OPT_3_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT) |
| #define VSC_VALUE_C_DATA_OPT_OPT_3_MASK (0xF000U) |
| #define VSC_VALUE_C_DATA_OPT_OPT_3_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_3_MASK) |
| #define VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT (12U) |
| #define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK) >> VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT) |
| #define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK (0xFFFFFFFFUL) |
| #define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT) & VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK) |
| #define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT (0U) |
| #define VSC_VALUE_C_SW_VALUE_C_SW_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_C_SW_VALUE_C_SW_MASK) >> VSC_VALUE_C_SW_VALUE_C_SW_SHIFT) |
| #define VSC_VALUE_C_SW_VALUE_C_SW_MASK (0xFFFFFFFFUL) |
| #define VSC_VALUE_C_SW_VALUE_C_SW_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_C_SW_VALUE_C_SW_SHIFT) & VSC_VALUE_C_SW_VALUE_C_SW_MASK) |
| #define VSC_VALUE_C_SW_VALUE_C_SW_SHIFT (0U) |
| #define VSC_VALUE_SW_READY_VALUE_SW_READY_GET | ( | x | ) | (((uint32_t)(x) & VSC_VALUE_SW_READY_VALUE_SW_READY_MASK) >> VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT) |
| #define VSC_VALUE_SW_READY_VALUE_SW_READY_MASK (0x1U) |
| #define VSC_VALUE_SW_READY_VALUE_SW_READY_SET | ( | x | ) | (((uint32_t)(x) << VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT) & VSC_VALUE_SW_READY_VALUE_SW_READY_MASK) |
| #define VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT (0U) |
1.9.1