ppi async sram config structure More...

#include <hpm_ppi.h>

Data Fields
uint32_t	base_address

uint32_t	size_in_byte

ppi_port_size_t	port_size

bool	ad_mux_mode

bool	cs_valid_polarity

bool	dm_valid_polarity

bool	addr_valid_polarity

uint8_t	adv_ctrl_pin

uint8_t	rel_ctrl_pin

uint8_t	wel_ctrl_pin

uint8_t	as_in_ns

uint8_t	ah_in_ns

uint8_t	rel_in_ns

uint8_t	reh_in_ns

uint8_t	wel_in_ns

uint8_t	weh_in_ns

Detailed Description

ppi async sram config structure

Field Documentation

◆ ad_mux_mode

bool ppi_async_sram_config_t::ad_mux_mode

addr and data mux mode

◆ addr_valid_polarity

bool ppi_async_sram_config_t::addr_valid_polarity

addr valid polarity

◆ adv_ctrl_pin

uint8_t ppi_async_sram_config_t::adv_ctrl_pin

adv ctrl pin number, 0 - 7

◆ ah_in_ns

uint8_t ppi_async_sram_config_t::ah_in_ns

address hold time

◆ as_in_ns

uint8_t ppi_async_sram_config_t::as_in_ns

address setup time

◆ base_address

uint32_t ppi_async_sram_config_t::base_address

external SRAM base address, should be 1MB aligned

◆ cs_valid_polarity

bool ppi_async_sram_config_t::cs_valid_polarity

cs valid polarity

◆ dm_valid_polarity

bool ppi_async_sram_config_t::dm_valid_polarity

dm valid polarity

◆ port_size

ppi_port_size_t ppi_async_sram_config_t::port_size

port size

◆ reh_in_ns

uint8_t ppi_async_sram_config_t::reh_in_ns

RE high time

◆ rel_ctrl_pin

uint8_t ppi_async_sram_config_t::rel_ctrl_pin

rel ctrl pin number, 0 - 7

◆ rel_in_ns

uint8_t ppi_async_sram_config_t::rel_in_ns

RE low time

◆ size_in_byte

uint32_t ppi_async_sram_config_t::size_in_byte

external SRAM size in byte

◆ weh_in_ns

uint8_t ppi_async_sram_config_t::weh_in_ns

WE high time

◆ wel_ctrl_pin

uint8_t ppi_async_sram_config_t::wel_ctrl_pin

wel ctrl pin number, 0 - 7

◆ wel_in_ns

uint8_t ppi_async_sram_config_t::wel_in_ns

WE low time

The documentation for this struct was generated from the following file:

components/ppi/hpm_ppi.h

Data Fields