hpm_pdgo_drv.h

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/*
 * Copyright (c) 2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_PDGO_DRV_H
#define HPM_PDGO_DRV_H
 
#include "hpm_common.h"
#include "hpm_pdgo_regs.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define DGO_GPR_WORD_COUNT                (8U)         
#define DGO_WAKEUP_COUNTER_TICKS_PER_SEC  (32768UL)    
#define DGO_TURNOFF_COUNTER_TICKS_PER_SEC (24000000UL) 
#define DGO_WAKEUP_TICK_IN_US             (1000000UL / DGO_WAKEUP_COUNTER_TICKS_PER_SEC)
#define DGO_TURNOFF_TICKS_PER_US          (DGO_TURNOFF_COUNTER_TICKS_PER_SEC / 1000000UL)
 
typedef enum {
    dgo_wakeup_wkup_pin = PDGO_WKUP_EN_WKUP_MASK,
    dgo_wakeup_software = PDGO_WKUP_EN_CYC_MASK,
    dgo_wakeup_wuio_pins = PDGO_WKUP_EN_WUIO_MASK,
    dgo_wakeup_pcap0 = PDGO_WKUP_EN_PCAP0_MASK,
    dgo_wakeup_pcnt0 = PDGO_WKUP_EN_PCNT0_MASK,
} dgo_wakeup_bit_mask_t; 
typedef enum {
    dgo_irq0_wkup_pin = PDGO_IRQ0_EN_WKUP_MASK,
    dgo_irq0_software = PDGO_IRQ0_EN_CYC_MASK,
    dgo_irq0_wuio0_pin = PDGO_IRQ0_EN_WUIO0_MASK,
    dgo_irq0_wuio1_pin = PDGO_IRQ0_EN_WUIO1_MASK,
    dgo_irq0_wuio2_pin = PDGO_IRQ0_EN_WUIO2_MASK,
    dgo_irq0_wuio3_pin = PDGO_IRQ0_EN_WUIO3_MASK,
} dgo_irq0_bit_mask_t; 
typedef enum {
    dgo_irq1_pcap0_period = PDGO_IRQ1_EN_PCAP0_PERIOD_MASK,
    dgo_irq1_pcap0_dump = PDGO_IRQ1_EN_PCAP0_DUMP_MASK,
    dgo_irq1_pcap0_match = PDGO_IRQ1_EN_PCAP0_MATCH_MASK,
    dgo_irq1_pcnt0_update = PDGO_IRQ1_EN_PCNT0_UPDATE_MASK,
    dgo_irq1_pcnt0_z_match = PDGO_IRQ1_EN_PCNT0_Z_MASK,
    dgo_irq1_pcnt0_h_match = PDGO_IRQ1_EN_PCNT0_HOME_MASK,
    dgo_irq1_pcnt0_cmp0_match = PDGO_IRQ1_EN_PCNT0_MATCH0_MASK,
    dgo_irq1_pcnt0_tacho = PDGO_IRQ1_EN_PCNT0_TACHO_MASK,
    dgo_irq1_pcnt0_dec_err = PDGO_IRQ1_EN_PCNT0_DECERR_MASK,
    dgo_irq1_pcnt0_seq_err = PDGO_IRQ1_EN_PCNT0_SEQERR_MASK,
} dgo_irq1_bit_mask_t; 
typedef enum {
    dgo_wuio_pin_0 = 0,
    dgo_wuio_pin_1 = 1,
    dgo_wuio_pin_2 = 2,
    dgo_wuio_pin_3 = 3,
} dgo_wuio_pin_num_t;
 
typedef enum {
    dgo_pcap_0 = 0,
} dgo_pcap_num_t;
 
typedef enum {
    dgo_pcnt_0 = 0,
} dgo_pcnt_num_t;
 
typedef enum {
    dgo_wuio_irq_disable = 0,
    dgo_wuio_irq_level_mode = 1,
    dgo_wuio_irq_rise_edge_mode = 2,
    dgo_wuio_irq_both_edge_mode = 3,
} dgo_wuio_irq_mode_t;
 
typedef enum {
    dgo_filter_mode_rapid_change = 0,
    dgo_filter_mode_delay = 1,
    dgo_filter_mode_stable_high = 2,
    dgo_filter_mode_stable_low = 3,
    dgo_filter_mode_bypass = 4,
} dgo_filter_mode_t;
 
typedef enum {
    dgo_pcap_match_disable = 0,
    dgo_pcap_match_mode_cnt_ge_cmp = 2,
    dgo_pcap_match_mode_cnt_le_cmp,
    dgo_pcap_match_mode_highdump_ge_cmp,
    dgo_pcap_match_mode_highdump_le_cmp,
    dgo_pcap_match_mode_lowdump_ge_cmp,
    dgo_pcap_match_mode_lowdump_le_cmp,
    dgo_pcap_match_mode_highdump_add_lowdump_ge_cmp,
    dgo_pcap_match_mode_highdump_add_lowdump_le_cmp,
    dgo_pcap_match_mode_abs_highdump_minus_lowdump_ge_cmp,
    dgo_pcap_match_mode_abs_highdump_minus_lowdump_le_cmp,
    dgo_pcap_match_mode_highdump_minus_lowdump_ge_cmp,
    dgo_pcap_match_mode_lowdump_minus_highdump_le_cmp,
    dgo_pcap_match_mode_lowdump_minus_highdump_ge_cmp,
    dgo_pcap_match_mode_highdump_minus_lowdump_le_cmp,
} dgo_pcap_match_mode_t;
 
typedef enum {
    dgo_pcap_dump_disable = 0,
    dgo_pcap_dump_wuio_rise_edge,
    dgo_pcap_dump_wuio_fall_edge,
    dgo_pcap_dump_cnt_finish,
} dgo_pcap_dump_mode_t;
 
typedef enum {
    dgo_pcap_cnt_up = 0,
    dgo_pcap_cnt_down,
} dgo_pcap_cnt_dir_t;
 
typedef enum {
    dgo_pcap_cnt_oneshot = 0,
    dgo_pcap_cnt_period,
} dgo_pcap_cnt_mode_t;
 
typedef enum {
    dgo_pcap_cnt_internal_clk = 0,
    dgo_pcap_cnt_wuio_rise_edge,
    dgo_pcap_cnt_wuio_fall_edge,
    dgo_pcap_cnt_wuio_both_edge,
} dgo_pcap_cnt_event_t;
 
typedef enum {
    dgo_pcnt_ab_4x = 0,
    dgo_pcnt_ab_2x,
    dgo_pcnt_ab_1x,
    dgo_pcnt_pd_1x = 4,
    dgo_pcnt_pd_f_1x,
    dgo_pcnt_pd_2x,
    dgo_pcnt_pd_f_2x,
    dgo_pcnt_ud_1x,
    dgo_pcnt_ud_f_1x,
    dgo_pcnt_ud_2x,
    dgo_pcnt_ud_f_2x,
    dgo_pcnt_ud_uvw_6x,
    dgo_pcnt_ud_uvw_6y,
} dgo_pcnt_decode_mode_t;
 
typedef enum {
    dgo_pcnt_z_disable = 0,
    dgo_pcnt_z_edge_mode,
    dgo_pcnt_z_level_mode_with_ab,
    dgo_pcnt_z_level_mode,
} dgo_pcnt_z_mode_t;
 
typedef enum {
    dgo_pcnt_h_disable = 0,
    dgo_pcnt_h_edge_mode,
    dgo_pcnt_h_level_mode_with_ab,
    dgo_pcnt_h_level_mode,
} dgo_pcnt_h_mode_t;
 
typedef enum {
    dgo_pcnt_dump_disable = 0,
    dgo_pcnt_dump_h_edge_mode,
    dgo_pcnt_dump_h_level_mode_with_ab,
    dgo_pcnt_dump_h_level_mode,
} dgo_pcnt_dump_mode_t;
 
typedef enum {
    dgo_pcnt_tacho_disable = 0,
    dgo_pcnt_tacho_period_mode,
    dgo_pcnt_tacho_travel_mode,
} dgo_pcnt_tacho_mode_t;
 
typedef enum {
    dgo_pcnt_cmp_disable = 0,
    dgo_pcnt_cmp_range_match_mode,
    dgo_pcnt_cmp_match_mode0,
    dgo_pcnt_cmp_match_mode1,
    dgo_pcnt_cmp_match_forward_mode0,
    dgo_pcnt_cmp_match_forward_mode1,
    dgo_pcnt_cmp_match_reverse_mode0,
    dgo_pcnt_cmp_match_reverse_mode1,
} dgo_pcnt_cmp_mode_t;
 
typedef enum {
    dgo_pcnt_cmp_src_line_phase = 0,
    dgo_pcnt_cmp_src_revolution_line_phase,
    dgo_pcnt_cmp_src_tacho_line,
    dgo_pcnt_cmp_src_tacho_time,
} dgo_pcnt_range_cmp_src_t;
 
typedef struct {
    bool enable;
    bool output_invert;
    bool output_init_value;
    uint16_t filter_length;
    dgo_filter_mode_t filter_mode;
    dgo_wuio_irq_mode_t irq_mode;
} dgo_wuio_filter_cfg_t;
 
typedef struct {
    bool enable;
    dgo_wuio_pin_num_t wuio_select;
    dgo_pcap_match_mode_t match_mode;
    dgo_pcap_dump_mode_t dump_mode;
    dgo_pcap_cnt_dir_t cnt_dir;
    dgo_pcap_cnt_mode_t cnt_mode;
    dgo_pcap_cnt_event_t cnt_event;
    uint16_t cmp_value;
    uint16_t period_value;
} dgo_pcap_cfg_t;
 
typedef union {
    uint8_t state;
    struct {
        uint8_t a_level : 1;
        uint8_t b_level : 1;
        uint8_t z_edge : 1;
        uint8_t h_level : 1;
        uint8_t   : 4;
    } level_mode;
    struct {
        uint8_t rise_forward : 1;
        uint8_t fall_reverse : 1;
        uint8_t fall_forward : 1;
        uint8_t rise_reverse : 1;
        uint8_t              : 4;
    } edge_mode;
} dgo_pcnt_sig_state_t;
 
typedef struct {
    uint8_t phase;
    uint32_t line;
    uint32_t revolution;
} dgo_pcnt_counter_t;
 
typedef struct {
    bool enable;
    bool dir_invert_en;
    uint8_t phase_bias;
    dgo_wuio_pin_num_t a_sel;
    dgo_wuio_pin_num_t b_sel;
    dgo_wuio_pin_num_t z_sel;
    dgo_wuio_pin_num_t h_sel;
    dgo_pcnt_decode_mode_t decode_mode;
    uint32_t resolution;
    dgo_pcnt_z_mode_t z_mode;
    dgo_pcnt_sig_state_t z_state;
    dgo_pcnt_h_mode_t h_mode;
    dgo_pcnt_sig_state_t h_state;
    dgo_pcnt_dump_mode_t dump_mode;
    dgo_pcnt_sig_state_t dump_state;
    dgo_pcnt_tacho_mode_t tacho_mode;
    uint16_t tacho_len;
    dgo_pcnt_cmp_mode_t cmp0_mode;
    dgo_pcnt_range_cmp_src_t range_cmp_src;
    uint32_t cmp0_value;
    uint32_t cmp1_value;
} dgo_pcnt_cfg_t;
 
static inline void pdgo_set_turnoff_counter(PDGO_Type *ptr, uint32_t counter)
{
    ptr->DGO_TURNOFF = counter;
}
 
static inline void pdgo_enable_software_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN |= PDGO_WKUP_EN_CYC_MASK;
}
 
static inline void pdgo_disable_software_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN &= ~PDGO_WKUP_EN_CYC_MASK;
}
 
static inline void pdgo_set_wakeup_counter(PDGO_Type *ptr, uint32_t counter)
{
    ptr->WKUP_CYC = 0;
    ptr->WAKEUP = counter;
}
 
static inline uint32_t pdgo_get_wakeup_counter(PDGO_Type *ptr)
{
    return ptr->WAKEUP;
}
 
static inline void pdgo_set_cycle_wakeup_counter(PDGO_Type *ptr, uint32_t counter)
{
    ptr->WKUP_CYC = counter;
}
 
static inline void pdgo_enable_wkup_pin_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN |= PDGO_WKUP_EN_WKUP_MASK;
}
 
static inline void pdgo_disable_wkup_pin_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN &= ~PDGO_WKUP_EN_WKUP_MASK;
}
 
static inline void pdgo_enable_wuio_pins_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN |= PDGO_WKUP_EN_WUIO_MASK;
}
 
static inline void pdgo_disable_wuio_pins_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN &= ~PDGO_WKUP_EN_WUIO_MASK;
}
 
static inline void pdgo_enable_pulse_capture0_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN |= PDGO_WKUP_EN_PCAP0_MASK;
}
 
static inline void pdgo_disable_pulse_capture0_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN &= ~PDGO_WKUP_EN_PCAP0_MASK;
}
 
static inline void pdgo_enable_pulse_counter0_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN |= PDGO_WKUP_EN_PCNT0_MASK;
}
 
static inline void pdgo_disable_pulse_counter0_wakeup(PDGO_Type *ptr)
{
    ptr->WKUP_EN &= ~PDGO_WKUP_EN_PCNT0_MASK;
}
 
static inline void pdgo_enable_wakeup_by_bit_mask(PDGO_Type *ptr, uint32_t mask)
{
    ptr->WKUP_EN |= mask;
}
 
static inline void pdgo_disable_wakeup_by_bit_mask(PDGO_Type *ptr, uint32_t mask)
{
    ptr->WKUP_EN &= ~mask;
}
 
static inline uint32_t pdgo_get_wakeup_status(PDGO_Type *ptr)
{
    return ptr->WKUP_STS;
}
 
static inline void pdgo_clear_wakeup_status(PDGO_Type *ptr, uint32_t mask)
{
    ptr->WKUP_STS = mask;
}
 
static inline void pdgo_disable_all_irq(PDGO_Type *ptr)
{
    ptr->IRQ0_EN = 0;
    ptr->IRQ1_EN = 0;
}
 
static inline void pdgo_enable_irq0_by_bit_mask(PDGO_Type *ptr, dgo_irq0_bit_mask_t mask)
{
    ptr->IRQ0_EN |= mask;
}
 
static inline void pdgo_disable_irq0_by_bit_mask(PDGO_Type *ptr, dgo_irq0_bit_mask_t mask)
{
    ptr->IRQ0_EN &= ~mask;
}
 
static inline uint32_t pdgo_get_irq0_en(PDGO_Type *ptr)
{
    return ptr->IRQ0_EN;
}
 
static inline uint32_t pdgo_get_irq0_status(PDGO_Type *ptr)
{
    return ptr->IRQ0_STS;
}
 
static inline void pdgo_clear_irq0_status(PDGO_Type *ptr, uint32_t mask)
{
    ptr->IRQ0_STS = mask;
}
 
static inline void pdgo_enable_irq1_by_bit_mask(PDGO_Type *ptr, dgo_irq1_bit_mask_t mask)
{
    ptr->IRQ1_EN |= mask;
}
 
static inline void pdgo_disable_irq1_by_bit_mask(PDGO_Type *ptr, dgo_irq1_bit_mask_t mask)
{
    ptr->IRQ1_EN &= ~mask;
}
 
static inline uint32_t pdgo_get_irq1_en(PDGO_Type *ptr)
{
    return ptr->IRQ1_EN;
}
 
static inline uint32_t pdgo_get_irq1_status(PDGO_Type *ptr)
{
    return ptr->IRQ1_STS;
}
 
static inline void pdgo_clear_irq1_status(PDGO_Type *ptr, uint32_t mask)
{
    ptr->IRQ1_STS = mask;
}
 
static inline void pdgo_enable_retention_mode(PDGO_Type *ptr)
{
    ptr->DGO_CTRL |= PDGO_DGO_CTRL_RET_MASK;
}
 
static inline bool pdgo_is_retention_mode_enabled(PDGO_Type *ptr)
{
    return ((ptr->DGO_CTRL & PDGO_DGO_CTRL_RET_MASK) != 0U);
}
 
static inline void pdgo_disable_retention_mode(PDGO_Type *ptr)
{
    ptr->DGO_CTRL &= ~PDGO_DGO_CTRL_RET_MASK;
}
 
static inline void pdgo_enable_pullup_resistor_for_reset_pin(PDGO_Type *ptr)
{
    ptr->PIN_CTRL &= ~PDGO_PIN_CTRL_RSTN_MASK;
}
 
static inline void pdgo_disable_pullup_resistor_for_reset_pin(PDGO_Type *ptr)
{
    ptr->PIN_CTRL |= PDGO_PIN_CTRL_RSTN_MASK;
}
 
static inline void pdgo_enable_pulldown_resistor_for_wakeup_pin(PDGO_Type *ptr)
{
    ptr->PIN_CTRL &= ~PDGO_PIN_CTRL_WKUP_MASK;
}
 
static inline void pdgo_disable_pulldown_resistor_for_wakeup_pin(PDGO_Type *ptr)
{
    ptr->PIN_CTRL |= PDGO_PIN_CTRL_WKUP_MASK;
}
 
static inline void pdgo_enable_pulldown_resistor_for_wuio_pin(PDGO_Type *ptr, dgo_wuio_pin_num_t num)
{
    ptr->PIN_CTRL &= ~(PDGO_PIN_CTRL_WUIO0_MASK << num);
}
 
static inline void pdgo_disable_pulldown_resistor_for_wuio_pin(PDGO_Type *ptr, dgo_wuio_pin_num_t num)
{
    ptr->PIN_CTRL |= (PDGO_PIN_CTRL_WUIO0_MASK << num);
}
 
static inline void pdgo_write_gpr(PDGO_Type *ptr, uint32_t index, uint32_t content)
{
    if (index < DGO_GPR_WORD_COUNT) {
        ptr->GPR[index] = content;
    }
}
 
static inline uint32_t pdgo_read_gpr(PDGO_Type *ptr, uint32_t index)
{
    uint32_t reg_val = 0;
    if (index < DGO_GPR_WORD_COUNT) {
        reg_val = ptr->GPR[index];
    }
    return reg_val;
}
 
static inline uint32_t pdgo_get_wakeup_counter_from_us(uint32_t us)
{
    return (us + DGO_WAKEUP_TICK_IN_US - 1U) / DGO_WAKEUP_TICK_IN_US;
}
 
static inline uint32_t pdgo_get_us_from_wakeup_counter(uint32_t counter)
{
    return (counter * DGO_WAKEUP_TICK_IN_US);
}
 
static inline uint32_t pdgo_get_turnoff_counter_from_us(uint32_t us)
{
    return (us * DGO_TURNOFF_TICKS_PER_US);
}
 
static inline uint32_t pdgo_get_us_from_turnoff_counter(uint32_t counter)
{
    return (counter + DGO_TURNOFF_TICKS_PER_US - 1U) / DGO_TURNOFF_TICKS_PER_US;
}
 
static inline void pdgo_set_wuio_pin_enable(PDGO_Type *ptr, dgo_wuio_pin_num_t num, bool enable)
{
    ptr->IOFILTER[num] = (ptr->IOFILTER[num] & ~PDGO_IOFILTER_EN_MASK) | PDGO_IOFILTER_EN_SET(enable);
}
 
static inline void pdgo_set_pcap_enable(PDGO_Type *ptr, dgo_pcap_num_t num, bool enable)
{
    ptr->PCAP[num].CTRL = (ptr->PCAP[num].CTRL & ~PDGO_PCAP_CTRL_EN_MASK) | PDGO_PCAP_CTRL_EN_SET(enable);
}
 
static inline void pdgo_set_pcap_counter_value(PDGO_Type *ptr, dgo_pcap_num_t num, uint16_t value)
{
    ptr->PCAP[num].COUNTER = value;
    while (PDGO_PCAP_COUNTER_COUNTER_GET(ptr->PCAP[num].COUNTER) != value) {
        ;
    }
}
 
static inline uint16_t pdgo_get_pcap_counter_value(PDGO_Type *ptr, dgo_pcap_num_t num)
{
    return PDGO_PCAP_COUNTER_COUNTER_GET(ptr->PCAP[num].COUNTER);
}
 
static inline void pdgo_set_pcnt_enable(PDGO_Type *ptr, dgo_pcnt_num_t num, bool enable)
{
    ptr->PCNT[num].CNT_CFG = (ptr->PCNT[num].CNT_CFG & ~PDGO_PCNT_CNT_CFG_EN_MASK) | PDGO_PCNT_CNT_CFG_EN_SET(enable);
}
 
static inline void pdgo_set_pcnt_cmp_mode(PDGO_Type *ptr, dgo_pcnt_num_t num, dgo_pcnt_cmp_mode_t mode)
{
    ptr->PCNT[num].HOMING_CFG = (ptr->PCNT[num].HOMING_CFG & ~PDGO_PCNT_HOMING_CFG_CMP0_MODE_MASK) | PDGO_PCNT_HOMING_CFG_CMP0_MODE_SET(mode);
}
 
static inline void pdgo_set_pcnt_cmp0_value(PDGO_Type *ptr, dgo_pcnt_num_t num, uint32_t value)
{
    ptr->PCNT[num].CMP0 = value;
    while (ptr->PCNT[num].CMP0 != value) {
        ;
    }
}
 
static inline void pdgo_set_pcnt_cmp1_value(PDGO_Type *ptr, dgo_pcnt_num_t num, uint32_t value)
{
    ptr->PCNT[num].CMP1 = value;
    while (ptr->PCNT[num].CMP1 != value) {
        ;
    }
}
 
static inline void pdgo_set_pcnt_raw_counter_value(PDGO_Type *ptr, dgo_pcnt_num_t num, uint32_t value)
{
    uint8_t bias = PDGO_PCNT_CNT_CFG_BIAS_GET(ptr->PCNT[num].CNT_CFG);
 
    ptr->PCNT[num].CNT = value;
    while (ptr->PCNT[num].CNT != (value + bias)) {
        ;
    }
}
 
static inline uint32_t pdgo_get_pcnt_raw_counter_value(PDGO_Type *ptr, dgo_pcnt_num_t num)
{
    return ptr->PCNT[num].CNT;
}
 
static inline void pdgo_enable_pcnt_dir_override(PDGO_Type *ptr, dgo_pcnt_num_t num)
{
    ptr->PCNT[num].CNT_CFG |= PDGO_PCNT_CNT_CFG_OVRD_MASK;
}
 
static inline void pdgo_disable_pcnt_dir_override(PDGO_Type *ptr, dgo_pcnt_num_t num)
{
    ptr->PCNT[num].CNT_CFG &= ~PDGO_PCNT_CNT_CFG_OVRD_MASK;
}
 
static inline void pdgo_set_pcnt_dir_override_value(PDGO_Type *ptr, dgo_pcnt_num_t num, bool reverse)
{
    ptr->PCNT[num].DIRECTION = (ptr->PCNT[num].DIRECTION & ~PDGO_PCNT_DIRECTION_DIR_MASK) | PDGO_PCNT_DIRECTION_DIR_SET(reverse);
}
 
void pdgo_config_wuio_filter(PDGO_Type *ptr, dgo_wuio_pin_num_t num, dgo_wuio_filter_cfg_t *cfg);
 
void pdgo_config_pcap(PDGO_Type *ptr, dgo_pcap_num_t num, dgo_pcap_cfg_t *cfg);
 
void pdgo_get_pcnt_defconfig(PDGO_Type *ptr, dgo_pcnt_num_t num, dgo_pcnt_cfg_t *cfg);
 
void pdgo_config_pcnt(PDGO_Type *ptr, dgo_pcnt_num_t num, dgo_pcnt_cfg_t *cfg);
 
void pdgo_get_pcnt_counter(PDGO_Type *ptr, dgo_pcnt_num_t num, dgo_pcnt_counter_t *counter);
 
uint32_t pdgo_convert_pcnt_counter(PDGO_Type *ptr, dgo_pcnt_num_t num, dgo_pcnt_counter_t *counter);
 
void pdgo_config_pcnt_range_compare(PDGO_Type *ptr, dgo_pcnt_num_t num, uint32_t cmp0, uint32_t  cmp1);
 
float pdgo_calc_pcnt_tacho_cycles_per_line(PDGO_Type *ptr, dgo_pcnt_num_t num);
 
#ifdef __cplusplus
}
#endif
 
#endif /* HPM_DGO_DRV_H */