|
| enum | qeiv2_work_mode {
qeiv2_work_mode_abz = 0
, qeiv2_work_mode_pd = 1
, qeiv2_work_mode_ud = 2
, qeiv2_work_mode_uvw = 3
,
qeiv2_work_mode_single = 4
, qeiv2_work_mode_sin = 5
, qeiv2_work_mode_sincos = 6
} |
| | qeiv2 work mode More...
|
| |
| enum | qeiv2_spd_tmr_content { qeiv2_spd_tmr_as_spd_tm = 0
, qeiv2_spd_tmr_as_pos_angle = 1
} |
| | spd and tmr read selection More...
|
| |
| enum | qeiv2_rotate_dir { qeiv2_rotate_dir_forward = 0
, qeiv2_rotate_dir_reverse = 1
} |
| | compare match rotate direction More...
|
| |
| enum | qeiv2_position_dir { qeiv2_pos_dir_decrease = 0
, qeiv2_pos_dir_increase = 1
} |
| | compare match position direction More...
|
| |
| enum | qeiv2_z_count_work_mode { qeiv2_z_count_inc_on_z_input_assert = 0
, qeiv2_z_count_inc_on_phase_count_max = 1
} |
| | counting mode of Z-phase counter More...
|
| |
| enum | qeiv2_counter_type { qeiv2_counter_type_z = 0
, qeiv2_counter_type_phase = 1
, qeiv2_counter_type_speed = 2
, qeiv2_counter_type_timer = 3
} |
| | counter type More...
|
| |
| enum | qeiv2_filter_mode {
qeiv2_filter_mode_bypass = 0
, qeiv2_filter_mode_burr = 4
, qeiv2_filter_mode_delay
, qeiv2_filter_mode_peak
,
qeiv2_filter_mode_valley
} |
| | filter mode More...
|
| |
| enum | qeiv2_filter_phase {
qeiv2_filter_phase_a = 0
, qeiv2_filter_phase_b
, qeiv2_filter_phase_z
, qeiv2_filter_phase_h
,
qeiv2_filter_phase_h2
, qeiv2_filter_phase_f
} |
| | filter type More...
|
| |
| enum | qeiv2_uvw_pos_opt { qeiv2_uvw_pos_opt_current = 0
, qeiv2_uvw_pos_opt_next
} |
| | uvw position option More...
|
| |
| enum | qeiv2_uvw_pos_sel { qeiv2_uvw_pos_sel_low = 0
, qeiv2_uvw_pos_sel_high
, qeiv2_uvw_pos_sel_edge
} |
| |
| enum | qeiv2_uvw_pos_idx {
qeiv2_uvw_pos0 = 0
, qeiv2_uvw_pos1
, qeiv2_uvw_pos2
, qeiv2_uvw_pos3
,
qeiv2_uvw_pos4
, qeiv2_uvw_pos5
} |
| |
| enum | qeiv2_adc_channel_t {
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_opamp1
, qeiv2_adc_chn_opamp0
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
} |
| |
| enum | qeiv2_adc_channel_t {
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_opamp1
, qeiv2_adc_chn_opamp0
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
} |
| |
| enum | qeiv2_adc_channel_t {
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_opamp1
, qeiv2_adc_chn_opamp0
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
} |
| |
| enum | qeiv2_adc_channel_t {
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_opamp1
, qeiv2_adc_chn_opamp0
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
,
qeiv2_adc_chn_0 = 0
, qeiv2_adc_chn_1
, qeiv2_adc_chn_2
, qeiv2_adc_chn_3
,
qeiv2_adc_chn_4
, qeiv2_adc_chn_5
, qeiv2_adc_chn_6
, qeiv2_adc_chn_7
,
qeiv2_adc_chn_8
, qeiv2_adc_chn_9
, qeiv2_adc_chn_10
, qeiv2_adc_chn_11
,
qeiv2_adc_chn_12
, qeiv2_adc_chn_13
, qeiv2_adc_chn_14
, qeiv2_adc_chn_15
} |
| |
|
| static void | qeiv2_load_counter_to_read_registers (QEIV2_Type *qeiv2_x) |
| | load phcnt, zcnt, spdcnt and tmrcnt into their read registers More...
|
| |
| static void | qeiv2_config_z_phase_counter_mode (QEIV2_Type *qeiv2_x, qeiv2_z_count_work_mode_t mode) |
| | config z phase counter increment and decrement mode More...
|
| |
| static void | qeiv2_config_phmax_phparam (QEIV2_Type *qeiv2_x, uint32_t phmax) |
| | config phase max value and phase param(for position calculation). It is recommended used without z-phase. If it has z-phase, you can only config phase param by used qeiv2_config_phparam() API. More...
|
| |
| static void | qeiv2_config_phmax (QEIV2_Type *qeiv2_x, uint32_t phmax) |
| | config phase max value More...
|
| |
| static void | qeiv2_config_phparam (QEIV2_Type *qeiv2_x, uint32_t phmax) |
| | config phase param for position calculation. More...
|
| |
| static void | qeiv2_config_z_phase_calibration (QEIV2_Type *qeiv2_x, uint32_t phidx, bool enable, bool ignore_ab) |
| | config phcnt calibration trigged by z phase More...
|
| |
| static void | qeiv2_pause_counter (QEIV2_Type *qeiv2_x, uint32_t counter_mask, bool enable) |
| | pause counter when pause assert More...
|
| |
| static void | qeiv2_pause_pos_counter_on_fault (QEIV2_Type *qeiv2_x, bool enable) |
| | pause pos counter when fault assert More...
|
| |
| static void | qeiv2_enable_snap (QEIV2_Type *qeiv2_x) |
| | enable load phcnt, zcnt, spdcnt and tmrcnt into their snap registers More...
|
| |
| static void | qeiv2_disable_snap (QEIV2_Type *qeiv2_x) |
| | disable snap More...
|
| |
| static void | qeiv2_reset_counter (QEIV2_Type *qeiv2_x) |
| | reset zcnt, spdcnt and tmrcnt to 0, reset phcnt to phidx. More...
|
| |
| static void | qeiv2_release_counter (QEIV2_Type *qeiv2_x) |
| | release counter. More...
|
| |
| static void | qeiv2_select_spd_tmr_register_content (QEIV2_Type *qeiv2_x, qeiv2_spd_tmr_content_t content) |
| | select spd and tmr register content More...
|
| |
| static bool | qeiv2_check_spd_tmr_as_pos_angle (QEIV2_Type *qeiv2_x) |
| | check spd and tmr register content as pos and angle More...
|
| |
| static void | qeiv2_set_work_mode (QEIV2_Type *qeiv2_x, qeiv2_work_mode_t mode) |
| | set qeiv2 work mode More...
|
| |
| static void | qeiv2_config_wdog (QEIV2_Type *qeiv2_x, uint32_t timeout, uint8_t clr_phcnt, bool enable) |
| | config watchdog More...
|
| |
| static void | qeiv2_enable_trig_out_trigger_event (QEIV2_Type *qeiv2_x, uint32_t event_mask) |
| | enable trig out trigger event More...
|
| |
| static void | qeiv2_disable_trig_out_trigger_event (QEIV2_Type *qeiv2_x, uint32_t event_mask) |
| | disable trig out trigger event More...
|
| |
| static void | qeiv2_enable_load_read_trigger_event (QEIV2_Type *qeiv2_x, uint32_t event_mask) |
| | enable load read trigger event More...
|
| |
| static void | qeiv2_disable_load_read_trigger_event (QEIV2_Type *qeiv2_x, uint32_t event_mask) |
| | disable load read trigger event More...
|
| |
| static void | qeiv2_enable_dma_request (QEIV2_Type *qeiv2_x, uint32_t mask) |
| | enable dma request More...
|
| |
| static void | qeiv2_disable_dma_request (QEIV2_Type *qeiv2_x, uint32_t mask) |
| | disable qeiv2 dma More...
|
| |
| static void | qeiv2_clear_status (QEIV2_Type *qeiv2_x, uint32_t mask) |
| | clear qeiv2 status register More...
|
| |
| static uint32_t | qeiv2_get_status (QEIV2_Type *qeiv2_x) |
| | get qeiv2 status More...
|
| |
| static bool | qeiv2_get_bit_status (QEIV2_Type *qeiv2_x, uint32_t mask) |
| | get qeiv2 bit status More...
|
| |
| static void | qeiv2_enable_irq (QEIV2_Type *qeiv2_x, uint32_t mask) |
| | enable qeiv2 irq More...
|
| |
| static void | qeiv2_disable_irq (QEIV2_Type *qeiv2_x, uint32_t mask) |
| | disable qeiv2 irq More...
|
| |
| static uint32_t | qeiv2_get_current_count (QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) |
| | get current counter value More...
|
| |
| static uint32_t | qeiv2_get_current_phase_phcnt (QEIV2_Type *qeiv2_x) |
| | get current phcnt value More...
|
| |
| static bool | qeiv2_get_current_phase_a_level (QEIV2_Type *qeiv2_x) |
| | get current a phase level More...
|
| |
| static bool | qeiv2_get_current_phase_b_level (QEIV2_Type *qeiv2_x) |
| | get current b phase level More...
|
| |
| static bool | qeiv2_get_current_phase_dir (QEIV2_Type *qeiv2_x) |
| | get current phase dir More...
|
| |
| static uint32_t | qeiv2_get_count_on_read_event (QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) |
| | get read event count value More...
|
| |
| static uint32_t | qeiv2_get_count_on_snap0_event (QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) |
| | read the value of each phase snapshot 0 counter More...
|
| |
| static uint32_t | qeiv2_get_count_on_snap1_event (QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) |
| | read the value of each phase snapshot 1 counter More...
|
| |
| static void | qeiv2_set_z_cmp_value (QEIV2_Type *qeiv2_x, uint32_t cmp) |
| | set zcnt compare value More...
|
| |
| static void | qeiv2_set_phcnt_cmp_value (QEIV2_Type *qeiv2_x, uint32_t cmp) |
| | set phcnt compare value More...
|
| |
| static void | qeiv2_set_spd_pos_cmp_value (QEIV2_Type *qeiv2_x, uint32_t cmp) |
| | set spdcnt or position compare value. It's selected by CR register rd_sel bit. More...
|
| |
| static void | qeiv2_set_cmp_match_option (QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp, bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir) |
| | set compare match options More...
|
| |
| static void | qeiv2_set_z_cmp2_value (QEIV2_Type *qeiv2_x, uint32_t cmp) |
| | set zcnt compare2 value More...
|
| |
| static void | qeiv2_set_phcnt_cmp2_value (QEIV2_Type *qeiv2_x, uint32_t cmp) |
| | set phcnt compare2 value More...
|
| |
| static void | qeiv2_set_spd_pos_cmp2_value (QEIV2_Type *qeiv2_x, uint32_t cmp) |
| | set spdcnt or position compare2 value. It's selected by CR register rd_sel bit. More...
|
| |
| static void | qeiv2_set_cmp2_match_option (QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp, bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir) |
| | set compare2 match options More...
|
| |
| static void | qeiv2_config_abz_uvw_signal_edge (QEIV2_Type *qeiv2_x, bool siga_en, bool sigb_en, bool sigz_en, bool posedge_en, bool negedge_en) |
| | config signal enablement and edge for speed and position measurement More...
|
| |
| static void | qeiv2_set_pulse0_num (QEIV2_Type *qeiv2_x, uint32_t pulse_num) |
| | set pulse0 value More...
|
| |
| static uint32_t | qeiv2_get_pulse0_cycle_snap0 (QEIV2_Type *qeiv2_x) |
| | get cycle0 snap0 value More...
|
| |
| static uint32_t | qeiv2_get_pulse0_cycle_snap1 (QEIV2_Type *qeiv2_x) |
| | get cycle0 snap1 value More...
|
| |
| static void | qeiv2_set_pulse1_num (QEIV2_Type *qeiv2_x, uint32_t pulse_num) |
| | set pulse1 value More...
|
| |
| static uint32_t | qeiv2_get_pulse1_cycle_snap0 (QEIV2_Type *qeiv2_x) |
| | get cycle1 snap0 value More...
|
| |
| static uint32_t | qeiv2_get_pulse1_cycle_snap1 (QEIV2_Type *qeiv2_x) |
| | get cycle1 snap1 value More...
|
| |
| static void | qeiv2_set_cycle0_num (QEIV2_Type *qeiv2_x, uint32_t cycle_num) |
| | set cycle0 value More...
|
| |
| static uint32_t | qeiv2_get_cycle0_pulse_snap0 (QEIV2_Type *qeiv2_x) |
| | get pulse0 snap0 value More...
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| static uint32_t | qeiv2_get_cycle0_pulse_snap1 (QEIV2_Type *qeiv2_x) |
| | get pulse0 snap1 value More...
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| static uint32_t | qeiv2_get_cycle0_pulse0cycle_snap0 (QEIV2_Type *qeiv2_x) |
| | get pulse0cycle snap0 value More...
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| static uint32_t | qeiv2_get_cycle0_pulse0cycle_snap1 (QEIV2_Type *qeiv2_x) |
| | get pulse0cycle snap1 value More...
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| static void | qeiv2_set_cycle1_num (QEIV2_Type *qeiv2_x, uint32_t cycle_num) |
| | set cycle1 value More...
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| static uint32_t | qeiv2_get_cycle1_pulse_snap0 (QEIV2_Type *qeiv2_x) |
| | get pulse1 snap0 value More...
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| static uint32_t | qeiv2_get_cycle1_pulse_snap1 (QEIV2_Type *qeiv2_x) |
| | get pulse1 snap1 value More...
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| static uint32_t | qeiv2_get_cycle1_pulse1cycle_snap0 (QEIV2_Type *qeiv2_x) |
| | get pulse1cycle snap0 value More...
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| static uint32_t | qeiv2_get_cycle1_pulse1cycle_snap1 (QEIV2_Type *qeiv2_x) |
| | get pulse1cycle snap1 value More...
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| static void | qeiv2_clear_counter_when_dir_chg (QEIV2_Type *qeiv2_x, bool enable) |
| | enable or disable clear counter if detect direction change More...
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| static void | qeiv2_config_adcx (QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable) |
| | adcx config More...
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| static void | qeiv2_config_adcy (QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable) |
| | adcy config More...
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| void | qeiv2_config_adcx_adcy_param (QEIV2_Type *qeiv2_x, float tan_delta, float cos_delta, float x_magnification, float y_magnification) |
| | Configures the orthogonal delta and magnification for ADCX and ADCY. More...
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| static void | qeiv2_set_adc_xy_delay (QEIV2_Type *qeiv2_x, uint32_t delay) |
| | set adcx and adcy delay More...
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| static void | qeiv2_set_position_threshold (QEIV2_Type *qeiv2_x, uint32_t threshold) |
| | set position threshold More...
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| static void | qeiv2_set_uvw_position_opt (QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_opt_t opt) |
| | set uvw position option More...
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| static void | qeiv2_set_uvw_position_sel (QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint8_t u_pos_sel, uint8_t v_pos_sel, uint8_t w_pos_sel, bool enable) |
| | set config uvw position More...
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| static void | qeiv2_set_uvw_position (QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint32_t pos) |
| | set uvw position More...
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| static void | qeiv2_set_z_phase (QEIV2_Type *qeiv2_x, uint32_t cnt) |
| | set z phase counter value More...
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| static uint32_t | qeiv2_get_z_phase (QEIV2_Type *qeiv2_x) |
| | get z phase counter value More...
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| static void | qeiv2_set_phase_cnt (QEIV2_Type *qeiv2_x, uint32_t cnt) |
| | set phase counter value More...
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| static uint32_t | qeiv2_get_phase_cnt (QEIV2_Type *qeiv2_x) |
| | get phase counter value More...
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| static void | qeiv2_update_phase_cnt (QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value) |
| | update phase counter value More...
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| static void | qeiv2_set_position (QEIV2_Type *qeiv2_x, uint32_t pos) |
| | set position value More...
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| static uint32_t | qeiv2_get_postion (QEIV2_Type *qeiv2_x) |
| | get position value More...
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| static void | qeiv2_update_position (QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value) |
| | update position value More...
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| static uint32_t | qeiv2_get_angle (QEIV2_Type *qeiv2_x) |
| | get angle value More...
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| static void | qeiv2_config_position_timeout (QEIV2_Type *qeiv2_x, uint32_t tm, bool enable) |
| | config position timeout for mmc module More...
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| void | qeiv2_config_mode (QEIV2_Type *qeiv2_x, qeiv2_mode_config_t *config) |
| | config qei mode More...
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| void | qeiv2_config_h_phase (QEIV2_Type *qeiv2_x, qeiv2_h_phase_config_t *config) |
| | config h phase signal More...
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| void | qeiv2_config_pause (QEIV2_Type *qeiv2_x, qeiv2_pause_config_t *config) |
| | config pause signal More...
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| hpm_stat_t | qeiv2_config_phcnt_cmp_match_condition (QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config) |
| | config phcnt compare match condition More...
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| hpm_stat_t | qeiv2_config_position_cmp_match_condition (QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config) |
| | config position compare match condition More...
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| hpm_stat_t | qeiv2_config_phcnt_cmp2_match_condition (QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config) |
| | config phcnt compare2 match condition More...
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| hpm_stat_t | qeiv2_config_position_cmp2_match_condition (QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config) |
| | config position compare2 match condition More...
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| void | qeiv2_get_uvw_position_defconfig (qeiv2_uvw_config_t *config) |
| | get uvw position default config More...
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| hpm_stat_t | qeiv2_config_uvw_position (QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config) |
| | config uvw position More...
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| void | qeiv2_config_filter (QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint32_t filtlen) |
| | config signal filter More...
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| uint8_t | qeiv2_adc_channel_convert (qeiv2_adc_channel_t adc_chn, uint8_t opamp_chn) |
| | Converts the given ADC channel to the corresponding QEI ADC channel. More...
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QEIV2 driver APIs.