HPM SDK
HPMicro Software Development Kit
hpm_interrupt.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef HPM_INTERRUPT_H
9 #define HPM_INTERRUPT_H
10 #include "hpm_common.h"
11 #include "hpm_csr_drv.h"
12 #include "hpm_plic_drv.h"
13 
20 #define M_MODE 0
21 #define S_MODE 1
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Machine mode API: these APIs are supposed to be called at machine mode */
28 
34 ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask)
35 {
36  set_csr(CSR_MSTATUS, mask);
37 }
38 
45 ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask)
46 {
47  return read_clear_csr(CSR_MSTATUS, mask);
48 }
49 
55 ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask)
56 {
57  set_csr(CSR_MSTATUS, mask);
58 }
59 
64 ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void)
65 {
66  set_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
67 }
68 
73 ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void)
74 {
75  clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
76 }
77 
81 ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void)
82 {
83  set_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
84 }
85 
90 ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void)
91 {
92  clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
93 }
94 
95 /*
96  * CPU Machine SWI control
97  *
98  * Machine SWI (MSIP) is connected to PLICSW irq 1.
99  */
100 #define PLICSWI 1
101 
106 ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void)
107 {
108  __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
109 }
110 
111 
116 ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void)
117 {
118  set_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
119 }
120 
121 
126 ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void)
127 {
128  clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
129 }
130 
131 
136 ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void)
137 {
138  __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI);
139 }
140 
145 ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void)
146 {
147  __plic_claim_irq(HPM_PLICSW_BASE, 0);
148 }
149 
154 ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void)
155 {
156  __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
157 }
158 
159 /*
160  * @brief Enable IRQ for machine mode
161  *
162  * @param[in] irq Interrupt number
163  */
164 #define intc_m_enable_irq(irq) \
165  intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq)
166 
167 /*
168  * @brief Disable IRQ for machine mode
169  *
170  * @param[in] irq Interrupt number
171  */
172 #define intc_m_disable_irq(irq) \
173  intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq)
174 
175 #define intc_m_set_threshold(threshold) \
176  intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold)
177 
178 #define intc_m_get_threshold() \
179  intc_get_threshold(HPM_PLIC_TARGET_M_MODE)
180 
181 /*
182  * @brief Complete IRQ for machine mode
183  *
184  * @param[in] irq Interrupt number
185  */
186 #define intc_m_complete_irq(irq) \
187  intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq)
188 
189 /*
190  * @brief Claim IRQ for machine mode
191  *
192  */
193 #define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE)
194 
195 /*
196  * @brief Enable IRQ for machine mode with priority
197  *
198  * @param[in] irq Interrupt number
199  * @param[in] priority Priority of interrupt
200  */
201 #define intc_m_enable_irq_with_priority(irq, priority) \
202  do { \
203  intc_set_irq_priority(irq, priority); \
204  intc_m_enable_irq(irq); \
205  } while (0)
206 
207 /*
208  * @brief Enable specific interrupt
209  *
210  * @param[in] target Target to handle specific interrupt
211  * @param[in] irq Interrupt number
212  */
213 ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq)
214 {
215  __plic_enable_irq(HPM_PLIC_BASE, target, irq);
216 }
217 
224 ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority)
225 {
226  __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority);
227 }
228 
235 ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq)
236 {
237  __plic_disable_irq(HPM_PLIC_BASE, target, irq);
238 }
239 
246 ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold)
247 {
248  __plic_set_threshold(HPM_PLIC_BASE, target, threshold);
249 }
250 
256 ATTR_ALWAYS_INLINE static inline uint32_t intc_get_threshold(uint32_t target)
257 {
258  return __plic_get_threshold(HPM_PLIC_BASE, target);
259 }
260 
267 ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target)
268 {
269  return __plic_claim_irq(HPM_PLIC_BASE, target);
270 }
271 
279 ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq)
280 {
281  __plic_complete_irq(HPM_PLIC_BASE, target, irq);
282 }
283 
284 /*
285  * Vectored based irq install and uninstall
286  */
287 /* Machine mode */
288 extern int __vector_table[];
289 extern void default_irq_entry(void);
290 
298 ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr)
299 {
300  __vector_table[irq] = isr;
301 }
302 
309 ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq)
310 {
311  __vector_table[irq] = (int) default_irq_entry;
312 }
313 
314 /*
315  * Inline nested irq entry/exit macros
316  */
317 /*
318  * @brief Save CSR
319  * @param[in] r Target CSR to be saved
320  */
321 #define SAVE_CSR(r) register long __##r = read_csr(r);
322 
323 /*
324  * @brief Restore macro
325  *
326  * @param[in] r Target CSR to be restored
327  */
328 #define RESTORE_CSR(r) write_csr(r, __##r);
329 
330 #if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH
331 #define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS)
332 #define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS)
333 #else
334 #define SAVE_MXSTATUS()
335 #define RESTORE_MXSTATUS()
336 #endif
337 
338 #ifdef __riscv_flen
339 #define SAVE_FCSR() register int __fcsr = read_fcsr();
340 #define RESTORE_FCSR() write_fcsr(__fcsr);
341 #else
342 #define SAVE_FCSR()
343 #define RESTORE_FCSR()
344 #endif
345 
346 #ifdef __riscv_dsp
347 #define SAVE_UCODE() SAVE_CSR(CSR_UCODE)
348 #define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE)
349 #else
350 #define SAVE_UCODE()
351 #define RESTORE_UCODE()
352 #endif
353 
354 #ifdef __riscv_flen
355 #if __riscv_flen == 32
356 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS + FCSR + UCODE (DSP) + MCCTL + 20 FPU caller registers */
357 #define CONTEXT_REG_NUM HPM_ALIGN_UP((4 * (22 + 20)), 16)
358 #else /* __riscv_flen = 64 */
359 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS + FCSR + UCODE (DSP) + MCCTL + 20 DFPU caller */
360 #define CONTEXT_REG_NUM HPM_ALIGN_UP((4 * (22 + 20 * 2)), 16)
361 #endif
362 
363 #else
364 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS + FCSR + UCODE (DSP) + MCCTL */
365 #define CONTEXT_REG_NUM HPM_ALIGN_UP((4 * 22), 16)
366 #endif
367 
368 #ifdef __riscv_flen
369 /*
370  * Save FPU caller registers:
371  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 22 in the stack
372  */
373 #if __riscv_flen == 32
374 #ifdef __ICCRISCV__
375 #define SAVE_FPU_CONTEXT() { \
376  __asm volatile("\n\
377  c.fswsp ft0, 22*4\n\
378  c.fswsp ft1, 23*4 \n\
379  c.fswsp ft2, 24*4 \n\
380  c.fswsp ft3, 25*4 \n\
381  c.fswsp ft4, 26*4 \n\
382  c.fswsp ft5, 27*4 \n\
383  c.fswsp ft6, 28*4 \n\
384  c.fswsp ft7, 29*4 \n\
385  c.fswsp fa0, 30*4 \n\
386  c.fswsp fa1, 31*4 \n\
387  c.fswsp fa2, 32*4 \n\
388  c.fswsp fa3, 33*4 \n\
389  c.fswsp fa4, 34*4 \n\
390  c.fswsp fa5, 35*4 \n\
391  c.fswsp fa6, 36*4 \n\
392  c.fswsp fa7, 37*4 \n\
393  c.fswsp ft8, 38*4 \n\
394  c.fswsp ft9, 39*4 \n\
395  c.fswsp ft10, 40*4 \n\
396  c.fswsp ft11, 41*4 \n");\
397 }
398 
399 /*
400  * Restore FPU caller registers:
401  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 22 in the stack
402  */
403 #define RESTORE_FPU_CONTEXT() { \
404  __asm volatile("\n\
405  c.flwsp ft0, 22*4\n\
406  c.flwsp ft1, 23*4 \n\
407  c.flwsp ft2, 24*4 \n\
408  c.flwsp ft3, 25*4 \n\
409  c.flwsp ft4, 26*4 \n\
410  c.flwsp ft5, 27*4 \n\
411  c.flwsp ft6, 28*4 \n\
412  c.flwsp ft7, 29*4 \n\
413  c.flwsp fa0, 30*4 \n\
414  c.flwsp fa1, 31*4 \n\
415  c.flwsp fa2, 32*4 \n\
416  c.flwsp fa3, 33*4 \n\
417  c.flwsp fa4, 34*4 \n\
418  c.flwsp fa5, 35*4 \n\
419  c.flwsp fa6, 36*4 \n\
420  c.flwsp fa7, 37*4 \n\
421  c.flwsp ft8, 38*4 \n\
422  c.flwsp ft9, 39*4 \n\
423  c.flwsp ft10, 40*4 \n\
424  c.flwsp ft11, 41*4 \n");\
425 }
426 #else /* __ICCRISCV__ not defined */
427 #define SAVE_FPU_CONTEXT() { \
428  __asm volatile("\n\
429  c.fswsp ft0, 22*4(sp)\n\
430  c.fswsp ft1, 23*4(sp) \n\
431  c.fswsp ft2, 24*4(sp) \n\
432  c.fswsp ft3, 25*4(sp) \n\
433  c.fswsp ft4, 26*4(sp) \n\
434  c.fswsp ft5, 27*4(sp) \n\
435  c.fswsp ft6, 28*4(sp) \n\
436  c.fswsp ft7, 29*4(sp) \n\
437  c.fswsp fa0, 30*4(sp) \n\
438  c.fswsp fa1, 31*4(sp) \n\
439  c.fswsp fa2, 32*4(sp) \n\
440  c.fswsp fa3, 33*4(sp) \n\
441  c.fswsp fa4, 34*4(sp) \n\
442  c.fswsp fa5, 35*4(sp) \n\
443  c.fswsp fa6, 36*4(sp) \n\
444  c.fswsp fa7, 37*4(sp) \n\
445  c.fswsp ft8, 38*4(sp) \n\
446  c.fswsp ft9, 39*4(sp) \n\
447  c.fswsp ft10, 40*4(sp) \n\
448  c.fswsp ft11, 41*4(sp) \n");\
449 }
450 
451 /*
452  * Restore FPU caller registers:
453  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 22 in the stack
454  */
455 #define RESTORE_FPU_CONTEXT() { \
456  __asm volatile("\n\
457  c.flwsp ft0, 22*4(sp)\n\
458  c.flwsp ft1, 23*4(sp) \n\
459  c.flwsp ft2, 24*4(sp) \n\
460  c.flwsp ft3, 25*4(sp) \n\
461  c.flwsp ft4, 26*4(sp) \n\
462  c.flwsp ft5, 27*4(sp) \n\
463  c.flwsp ft6, 28*4(sp) \n\
464  c.flwsp ft7, 29*4(sp) \n\
465  c.flwsp fa0, 30*4(sp) \n\
466  c.flwsp fa1, 31*4(sp) \n\
467  c.flwsp fa2, 32*4(sp) \n\
468  c.flwsp fa3, 33*4(sp) \n\
469  c.flwsp fa4, 34*4(sp) \n\
470  c.flwsp fa5, 35*4(sp) \n\
471  c.flwsp fa6, 36*4(sp) \n\
472  c.flwsp fa7, 37*4(sp) \n\
473  c.flwsp ft8, 38*4(sp) \n\
474  c.flwsp ft9, 39*4(sp) \n\
475  c.flwsp ft10, 40*4(sp) \n\
476  c.flwsp ft11, 41*4(sp) \n");\
477 }
478 #endif
479 #else /*__riscv_flen == 64*/
480 #ifdef __ICCRISCV__
481 #define SAVE_FPU_CONTEXT() { \
482  __asm volatile("\n\
483  c.fsdsp ft0, 22*4\n\
484  c.fsdsp ft1, 24*4 \n\
485  c.fsdsp ft2, 26*4 \n\
486  c.fsdsp ft3, 28*4 \n\
487  c.fsdsp ft4, 30*4 \n\
488  c.fsdsp ft5, 32*4 \n\
489  c.fsdsp ft6, 34*4 \n\
490  c.fsdsp ft7, 36*4 \n\
491  c.fsdsp fa0, 38*4 \n\
492  c.fsdsp fa1, 40*4 \n\
493  c.fsdsp fa2, 42*4 \n\
494  c.fsdsp fa3, 44*4 \n\
495  c.fsdsp fa4, 46*4 \n\
496  c.fsdsp fa5, 48*4 \n\
497  c.fsdsp fa6, 50*4 \n\
498  c.fsdsp fa7, 52*4 \n\
499  c.fsdsp ft8, 54*4 \n\
500  c.fsdsp ft9, 56*4 \n\
501  c.fsdsp ft10, 58*4 \n\
502  c.fsdsp ft11, 60*4 \n");\
503 }
504 
505 /*
506  * Restore FPU caller registers:
507  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 22 in the stack
508  */
509 #define RESTORE_FPU_CONTEXT() { \
510  __asm volatile("\n\
511  c.fldsp ft0, 22*4\n\
512  c.fldsp ft1, 24*4 \n\
513  c.fldsp ft2, 26*4 \n\
514  c.fldsp ft3, 28*4 \n\
515  c.fldsp ft4, 30*4 \n\
516  c.fldsp ft5, 32*4 \n\
517  c.fldsp ft6, 34*4 \n\
518  c.fldsp ft7, 36*4 \n\
519  c.fldsp fa0, 38*4 \n\
520  c.fldsp fa1, 40*4 \n\
521  c.fldsp fa2, 42*4 \n\
522  c.fldsp fa3, 44*4 \n\
523  c.fldsp fa4, 46*4 \n\
524  c.fldsp fa5, 48*4 \n\
525  c.fldsp fa6, 50*4 \n\
526  c.fldsp fa7, 52*4 \n\
527  c.fldsp ft8, 54*4 \n\
528  c.fldsp ft9, 56*4 \n\
529  c.fldsp ft10, 58*4 \n\
530  c.fldsp ft11, 60*4 \n");\
531 }
532 #else /*__riscv_flen == 64*/
533 #define SAVE_FPU_CONTEXT() { \
534  __asm volatile("\n\
535  c.fsdsp ft0, 22*4(sp)\n\
536  c.fsdsp ft1, 24*4(sp) \n\
537  c.fsdsp ft2, 26*4(sp) \n\
538  c.fsdsp ft3, 28*4(sp) \n\
539  c.fsdsp ft4, 30*4(sp) \n\
540  c.fsdsp ft5, 32*4(sp) \n\
541  c.fsdsp ft6, 34*4(sp) \n\
542  c.fsdsp ft7, 36*4(sp) \n\
543  c.fsdsp fa0, 38*4(sp) \n\
544  c.fsdsp fa1, 40*4(sp) \n\
545  c.fsdsp fa2, 42*4(sp) \n\
546  c.fsdsp fa3, 44*4(sp) \n\
547  c.fsdsp fa4, 46*4(sp) \n\
548  c.fsdsp fa5, 48*4(sp) \n\
549  c.fsdsp fa6, 50*4(sp) \n\
550  c.fsdsp fa7, 52*4(sp) \n\
551  c.fsdsp ft8, 54*4(sp) \n\
552  c.fsdsp ft9, 56*4(sp) \n\
553  c.fsdsp ft10, 58*4(sp) \n\
554  c.fsdsp ft11, 60*4(sp) \n");\
555 }
556 
557 /*
558  * Restore FPU caller registers:
559  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 22 in the stack
560  */
561 #define RESTORE_FPU_CONTEXT() { \
562  __asm volatile("\n\
563  c.fldsp ft0, 22*4(sp)\n\
564  c.fldsp ft1, 24*4(sp) \n\
565  c.fldsp ft2, 26*4(sp) \n\
566  c.fldsp ft3, 28*4(sp) \n\
567  c.fldsp ft4, 30*4(sp) \n\
568  c.fldsp ft5, 32*4(sp) \n\
569  c.fldsp ft6, 34*4(sp) \n\
570  c.fldsp ft7, 36*4(sp) \n\
571  c.fldsp fa0, 38*4(sp) \n\
572  c.fldsp fa1, 40*4(sp) \n\
573  c.fldsp fa2, 42*4(sp) \n\
574  c.fldsp fa3, 44*4(sp) \n\
575  c.fldsp fa4, 46*4(sp) \n\
576  c.fldsp fa5, 48*4(sp) \n\
577  c.fldsp fa6, 50*4(sp) \n\
578  c.fldsp fa7, 52*4(sp) \n\
579  c.fldsp ft8, 54*4(sp) \n\
580  c.fldsp ft9, 56*4(sp) \n\
581  c.fldsp ft10, 58*4(sp) \n\
582  c.fldsp ft11, 60*4(sp) \n");\
583 }
584 #endif
585 #endif
586 #else
587 #define SAVE_FPU_CONTEXT()
588 #define RESTORE_FPU_CONTEXT()
589 #endif
590 
591 #ifdef __ICCRISCV__
595 #define SAVE_CALLER_CONTEXT() { \
596  __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\
597  __asm volatile("\n\
598  c.swsp ra, 0*4 \n\
599  c.swsp t0, 1*4 \n\
600  c.swsp t1, 2*4 \n\
601  c.swsp t2, 3*4 \n\
602  c.swsp s1, 4*4 \n\
603  c.swsp a0, 5*4 \n\
604  c.swsp a1, 6*4 \n\
605  c.swsp a2, 7*4 \n\
606  c.swsp a3, 8*4 \n\
607  c.swsp a4, 9*4 \n\
608  c.swsp a5, 10*4 \n\
609  c.swsp a6, 11*4 \n\
610  c.swsp a7, 12*4 \n\
611  c.swsp s2, 13*4 \n\
612  c.swsp s3, 14*4 \n\
613  c.swsp s4, 15*4 \n\
614  c.swsp s5, 16*4 \n\
615  c.swsp s6, 17*4 \n\
616  c.swsp t3, 18*4 \n\
617  c.swsp t4, 19*4 \n\
618  c.swsp t5, 20*4 \n\
619  c.swsp t6, 21*4"); \
620  SAVE_FPU_CONTEXT(); \
621 }
622 
626 #define RESTORE_CALLER_CONTEXT() { \
627  __asm volatile("\n\
628  c.lwsp ra, 0*4 \n\
629  c.lwsp t0, 1*4 \n\
630  c.lwsp t1, 2*4 \n\
631  c.lwsp t2, 3*4 \n\
632  c.lwsp s1, 4*4 \n\
633  c.lwsp a0, 5*4 \n\
634  c.lwsp a1, 6*4 \n\
635  c.lwsp a2, 7*4 \n\
636  c.lwsp a3, 8*4 \n\
637  c.lwsp a4, 9*4 \n\
638  c.lwsp a5, 10*4 \n\
639  c.lwsp a6, 11*4 \n\
640  c.lwsp a7, 12*4 \n\
641  c.lwsp s2, 13*4 \n\
642  c.lwsp s3, 14*4 \n\
643  c.lwsp s4, 15*4 \n\
644  c.lwsp s5, 16*4 \n\
645  c.lwsp s6, 17*4 \n\
646  c.lwsp t3, 18*4 \n\
647  c.lwsp t4, 19*4 \n\
648  c.lwsp t5, 20*4 \n\
649  c.lwsp t6, 21*4 \n");\
650  RESTORE_FPU_CONTEXT(); \
651  __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\
652 }
653 #else
657 #define SAVE_CALLER_CONTEXT() { \
658  __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\
659  __asm volatile("\n\
660  c.swsp ra, 0*4(sp) \n\
661  c.swsp t0, 1*4(sp) \n\
662  c.swsp t1, 2*4(sp) \n\
663  c.swsp t2, 3*4(sp) \n\
664  c.swsp s1, 4*4(sp) \n\
665  c.swsp a0, 5*4(sp) \n\
666  c.swsp a1, 6*4(sp) \n\
667  c.swsp a2, 7*4(sp) \n\
668  c.swsp a3, 8*4(sp) \n\
669  c.swsp a4, 9*4(sp) \n\
670  c.swsp a5, 10*4(sp) \n\
671  c.swsp a6, 11*4(sp) \n\
672  c.swsp a7, 12*4(sp) \n\
673  c.swsp s2, 13*4(sp) \n\
674  c.swsp s3, 14*4(sp) \n\
675  c.swsp s4, 15*4(sp) \n\
676  c.swsp s5, 16*4(sp) \n\
677  c.swsp s6, 17*4(sp) \n\
678  c.swsp t3, 18*4(sp) \n\
679  c.swsp t4, 19*4(sp) \n\
680  c.swsp t5, 20*4(sp) \n\
681  c.swsp t6, 21*4(sp)"); \
682  SAVE_FPU_CONTEXT(); \
683 }
684 
688 #define RESTORE_CALLER_CONTEXT() { \
689  __asm volatile("\n\
690  c.lwsp ra, 0*4(sp) \n\
691  c.lwsp t0, 1*4(sp) \n\
692  c.lwsp t1, 2*4(sp) \n\
693  c.lwsp t2, 3*4(sp) \n\
694  c.lwsp s1, 4*4(sp) \n\
695  c.lwsp a0, 5*4(sp) \n\
696  c.lwsp a1, 6*4(sp) \n\
697  c.lwsp a2, 7*4(sp) \n\
698  c.lwsp a3, 8*4(sp) \n\
699  c.lwsp a4, 9*4(sp) \n\
700  c.lwsp a5, 10*4(sp) \n\
701  c.lwsp a6, 11*4(sp) \n\
702  c.lwsp a7, 12*4(sp) \n\
703  c.lwsp s2, 13*4(sp) \n\
704  c.lwsp s3, 14*4(sp) \n\
705  c.lwsp s4, 15*4(sp) \n\
706  c.lwsp s5, 16*4(sp) \n\
707  c.lwsp s6, 17*4(sp) \n\
708  c.lwsp t3, 18*4(sp) \n\
709  c.lwsp t4, 19*4(sp) \n\
710  c.lwsp t5, 20*4(sp) \n\
711  c.lwsp t6, 21*4(sp) \n");\
712  RESTORE_FPU_CONTEXT(); \
713  __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\
714 }
715 #endif
716 
717 #ifdef __riscv_flen
718 #define SAVE_FPU_STATE() { \
719  __asm volatile("frcsr s1\n"); \
720 }
721 
722 #define RESTORE_FPU_STATE() { \
723  __asm volatile("fscsr s1\n"); \
724 }
725 #else
726 #define SAVE_FPU_STATE()
727 #define RESTORE_FPU_STATE()
728 #endif
729 
730 #ifdef __riscv_dsp
731 /*
732  * @brief Save DSP context
733  */
734 #define SAVE_DSP_CONTEXT() { \
735  __asm volatile("csrrs s4, %0, x0\n" ::"i"(CSR_UCODE):); \
736 }
737 /*
738  * @brief Restore DSP context
739  */
740 #define RESTORE_DSP_CONTEXT() {\
741  __asm volatile("csrw %0, s4\n" ::"i"(CSR_UCODE):); \
742 }
743 
744 #else
745 #define SAVE_DSP_CONTEXT()
746 #define RESTORE_DSP_CONTEXT()
747 #endif
748 
749 /*
750  * @brief Save MCCTL context
751  */
752 #define SAVE_MCCTL_CONTEXT() { \
753  __asm volatile("csrrs s5, %0, x0\n" ::"i"(CSR_MCCTLBEGINADDR):); \
754  __asm volatile("csrrs s6, %0, x0\n" ::"i"(CSR_MCCTLDATA):); \
755 }
756 /*
757  * @brief Restore MCCTL context
758  */
759 #define RESTORE_MCCTL_CONTEXT() {\
760  __asm volatile("csrw %0, s6\n" ::"i"(CSR_MCCTLDATA):); \
761  __asm volatile("csrw %0, s5\n" ::"i"(CSR_MCCTLBEGINADDR):); \
762 }
763 
764 /*
765  * @brief Enter Nested IRQ Handling
766  * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
767  * MCAUSE - word offset 16 (not used in the vectored mode)
768  * EPC - word offset 17
769  * MSTATUS = word offset 18
770  * MXSTATUS = word offset 19
771  */
772 #define ENTER_NESTED_IRQ_HANDLING_M() { \
773  __asm volatile("\n\
774  csrr s2, mepc \n\
775  csrr s3, mstatus \n");\
776  SAVE_FPU_STATE(); \
777  SAVE_DSP_CONTEXT(); \
778  SAVE_MCCTL_CONTEXT(); \
779  __asm volatile("csrsi mstatus, 8"); \
780 }
781 
782 /*
783  * @brief Complete IRQ Handling
784  */
785 #define COMPLETE_IRQ_HANDLING_M(irq_num) { \
786  __asm volatile("csrci mstatus, 8"); \
787  __asm volatile("lui a4, 0xe4200"); \
788  __asm volatile("li a3, %0" : : "i" (irq_num) :); \
789  __asm volatile("sw a3, 4(a4)"); \
790 }
791 
792 /*
793  * @brief Exit Nested IRQ Handling
794  * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
795  * MCAUSE - word offset 16 (not used in the vectored mode)
796  * EPC - word offset 17
797  * MSTATUS = word offset 18
798  * MXSTATUS = word offset 19
799  */
800 #define EXIT_NESTED_IRQ_HANDLING_M() { \
801  __asm volatile("\n\
802  csrw mstatus, s3 \n\
803  csrw mepc, s2 \n");\
804  RESTORE_FPU_STATE(); \
805  RESTORE_DSP_CONTEXT(); \
806  RESTORE_MCCTL_CONTEXT(); \
807 }
808 
809 /* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */
810 #define NESTED_IRQ_ENTER() \
811  SAVE_CSR(CSR_MEPC) \
812  SAVE_CSR(CSR_MSTATUS) \
813  SAVE_MXSTATUS() \
814  SAVE_FCSR() \
815  SAVE_UCODE() \
816  set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK);
817 
818 /* @brief Nested IRQ exit macro : Restore CSRs */
819 #define NESTED_IRQ_EXIT() \
820  RESTORE_CSR(CSR_MSTATUS) \
821  RESTORE_CSR(CSR_MEPC) \
822  RESTORE_MXSTATUS() \
823  RESTORE_FCSR() \
824  RESTORE_UCODE()
825 
826 #ifdef __cplusplus
827 #define HPM_EXTERN_C extern "C"
828 #else
829 #define HPM_EXTERN_C
830 #endif
831 
832 #define ISR_NAME_M(irq_num) default_isr_##irq_num
839 #if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)
840 #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS
841 #define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num
842 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
843 void isr(void) __attribute__((section(".isr_vector"))); \
844 HPM_EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \
845 void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \
846 { \
847  isr();\
848 }
849 
850 #else
851 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
852 void isr(void) __attribute__((section(".isr_vector")));\
853 HPM_EXTERN_C HPM_ATTR_MACHINE_INTERRUPT void ISR_NAME_M(irq_num)(void);\
854 HPM_ATTR_MACHINE_INTERRUPT void ISR_NAME_M(irq_num)(void) \
855 { \
856  SAVE_CALLER_CONTEXT(); \
857  ENTER_NESTED_IRQ_HANDLING_M();\
858  __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\
859  __asm volatile("jalr t1\n");\
860  COMPLETE_IRQ_HANDLING_M(irq_num);\
861  EXIT_NESTED_IRQ_HANDLING_M();\
862  RESTORE_CALLER_CONTEXT();\
863  __asm volatile("fence io, io");\
864 }
865 #endif
866 #else
867 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
868 void isr(void) __attribute__((section(".isr_vector")));\
869 HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\
870 void ISR_NAME_M(irq_num)(void) \
871 { \
872  isr(); \
873 }
874 #endif
875 
876 
882 #define SDK_DECLARE_MCHTMR_ISR(isr) \
883 void isr(void) __attribute__((section(".isr_vector")));\
884 HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \
885 void mchtmr_isr(void) \
886 { \
887  isr();\
888 }
889 
895 #define SDK_DECLARE_SWI_ISR(isr)\
896 void isr(void) __attribute__((section(".isr_vector")));\
897 HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \
898 void swi_isr(void) \
899 { \
900  isr();\
901 }
902 
903 
904 #ifdef __cplusplus
905 }
906 #endif
907 
911 #endif /* HPM_INTERRUPT_H */
CSR_MIE_MEIE_MASK
#define CSR_MIE_MEIE_MASK
Definition: hpm_csr_regs.h:734
CSR_MSTATUS
#define CSR_MSTATUS
Definition: hpm_csr_regs.h:21
CSR_MIE_MTIE_MASK
#define CSR_MIE_MTIE_MASK
Definition: hpm_csr_regs.h:758
CSR_MIE
#define CSR_MIE
Definition: hpm_csr_regs.h:23
CSR_MIE_MSIE_MASK
#define CSR_MIE_MSIE_MASK
Definition: hpm_csr_regs.h:782
HPM_PLICSW_BASE
#define HPM_PLICSW_BASE
Definition: hpm_soc.h:52
HPM_PLIC_BASE
#define HPM_PLIC_BASE
Definition: hpm_soc.h:38
intc_complete_irq
static ATTR_ALWAYS_INLINE void intc_complete_irq(uint32_t target, uint32_t irq)
Complete IRQ.
Definition: hpm_interrupt.h:279
enable_global_irq
static ATTR_ALWAYS_INLINE void enable_global_irq(uint32_t mask)
Enable global IRQ with mask.
Definition: hpm_interrupt.h:34
intc_m_disable_swi
static ATTR_ALWAYS_INLINE void intc_m_disable_swi(void)
Disable software interrupt.
Definition: hpm_interrupt.h:126
disable_irq_from_intc
static ATTR_ALWAYS_INLINE void disable_irq_from_intc(void)
Disable IRQ from interrupt controller.
Definition: hpm_interrupt.h:73
intc_set_irq_priority
static ATTR_ALWAYS_INLINE void intc_set_irq_priority(uint32_t irq, uint32_t priority)
Set interrupt priority.
Definition: hpm_interrupt.h:224
intc_disable_irq
static ATTR_ALWAYS_INLINE void intc_disable_irq(uint32_t target, uint32_t irq)
Disable specific interrupt.
Definition: hpm_interrupt.h:235
intc_m_trigger_swi
static ATTR_ALWAYS_INLINE void intc_m_trigger_swi(void)
Trigger software interrupt.
Definition: hpm_interrupt.h:136
install_isr
static ATTR_ALWAYS_INLINE void install_isr(uint32_t irq, uint32_t isr)
Install ISR for certain IRQ for ram based vector table.
Definition: hpm_interrupt.h:298
enable_irq_from_intc
static ATTR_ALWAYS_INLINE void enable_irq_from_intc(void)
Enable IRQ from interrupt controller.
Definition: hpm_interrupt.h:64
restore_global_irq
static ATTR_ALWAYS_INLINE void restore_global_irq(uint32_t mask)
Restore global IRQ with mask.
Definition: hpm_interrupt.h:55
intc_enable_irq
static ATTR_ALWAYS_INLINE void intc_enable_irq(uint32_t target, uint32_t irq)
Definition: hpm_interrupt.h:213
disable_mchtmr_irq
static ATTR_ALWAYS_INLINE void disable_mchtmr_irq(void)
Disable machine timer IRQ.
Definition: hpm_interrupt.h:90
intc_m_init_swi
static ATTR_ALWAYS_INLINE void intc_m_init_swi(void)
Initialize software interrupt.
Definition: hpm_interrupt.h:106
intc_m_enable_swi
static ATTR_ALWAYS_INLINE void intc_m_enable_swi(void)
Enable software interrupt.
Definition: hpm_interrupt.h:116
intc_m_complete_swi
static ATTR_ALWAYS_INLINE void intc_m_complete_swi(void)
Complete software interrupt.
Definition: hpm_interrupt.h:154
intc_get_threshold
static ATTR_ALWAYS_INLINE uint32_t intc_get_threshold(uint32_t target)
Get interrupt threshold.
Definition: hpm_interrupt.h:256
intc_set_threshold
static ATTR_ALWAYS_INLINE void intc_set_threshold(uint32_t target, uint32_t threshold)
Set interrupt threshold.
Definition: hpm_interrupt.h:246
uninstall_isr
static ATTR_ALWAYS_INLINE void uninstall_isr(uint32_t irq)
Uninstall ISR for certain IRQ for ram based vector table.
Definition: hpm_interrupt.h:309
intc_claim_irq
static ATTR_ALWAYS_INLINE uint32_t intc_claim_irq(uint32_t target)
Claim IRQ.
Definition: hpm_interrupt.h:267
intc_m_claim_swi
static ATTR_ALWAYS_INLINE void intc_m_claim_swi(void)
Claim software interrupt.
Definition: hpm_interrupt.h:145
disable_global_irq
static ATTR_ALWAYS_INLINE uint32_t disable_global_irq(uint32_t mask)
Disable global IRQ with mask and return mstatus.
Definition: hpm_interrupt.h:45
enable_mchtmr_irq
static ATTR_ALWAYS_INLINE void enable_mchtmr_irq(void)
Enable machine timer IRQ.
Definition: hpm_interrupt.h:81
hpm_plic_drv.h
default_irq_entry
void default_irq_entry(void)
PLICSWI
#define PLICSWI
Definition: hpm_interrupt.h:100
HPM_PLIC_TARGET_M_MODE
#define HPM_PLIC_TARGET_M_MODE
Definition: hpm_plic_drv.h:17
hpm_common.h
hpm_csr_drv.h
set_csr
#define set_csr(csr_num, bit)
set bits in csr
Definition: riscv_core.h:58
clear_csr
#define clear_csr(csr_num, bit)
clear bits in csr
Definition: riscv_core.h:30
read_clear_csr
#define read_clear_csr(csr_num, bit)
read and clear bits in csr
Definition: riscv_core.h:40