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HPM SDK
HPMicro Software Development Kit
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HPM SDK
HPMicro Software Development Kit
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#include "hpm_soc_irq.h"#include "hpm_common.h"#include "hpm_gpio_regs.h"#include "hpm_plic_regs.h"#include "hpm_mchtmr_regs.h"#include "hpm_plic_sw_regs.h"#include "hpm_gptmr_regs.h"#include "hpm_uart_regs.h"#include "hpm_i2c_regs.h"#include "hpm_spi_regs.h"#include "hpm_crc_regs.h"#include "hpm_tsns_regs.h"#include "hpm_mbx_regs.h"#include "hpm_ewdg_regs.h"#include "hpm_dmamux_regs.h"#include "hpm_dmav2_regs.h"#include "hpm_gpiom_regs.h"#include "hpm_synt_regs.h"#include "hpm_trgm_regs.h"#include "hpm_usb_regs.h"#include "hpm_sec_regs.h"#include "hpm_mon_regs.h"#include "hpm_otp_regs.h"#include "hpm_keym_regs.h"#include "hpm_adc16_regs.h"#include "hpm_acmp_regs.h"#include "hpm_sysctl_regs.h"#include "hpm_ioc_regs.h"#include "hpm_pllctlv2_regs.h"#include "hpm_ppor_regs.h"#include "hpm_pcfg_regs.h"#include "hpm_pgpr_regs.h"#include "hpm_pdgo_regs.h"#include "riscv/riscv_core.h"#include "hpm_csr_regs.h"#include "hpm_interrupt.h"#include "hpm_misc.h"#include "hpm_otp_table.h"#include "hpm_dmamux_src.h"#include "hpm_trgmmux_src.h"#include "hpm_iomux.h"#include "hpm_pmic_iomux.h"Go to the source code of this file.
| #define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) |
| #define HPM_ACMP_BASE (0xF30B0000UL) |
| #define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) |
| #define HPM_ADC0_BASE (0xF3080000UL) |
| #define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) |
| #define HPM_CRC_BASE (0xF0080000UL) |
| #define HPM_DM_BASE (0x30000000UL) |
| #define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) |
| #define HPM_DMAMUX_BASE (0xF00C4000UL) |
| #define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) |
| #define HPM_EWDG0_BASE (0xF00B0000UL) |
| #define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) |
| #define HPM_EWDG1_BASE (0xF00B4000UL) |
| #define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) |
| #define HPM_FGPIO_BASE (0xC0000UL) |
| #define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) |
| #define HPM_GPIO0_BASE (0xF00D0000UL) |
| #define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) |
| #define HPM_GPIOM_BASE (0xF00D8000UL) |
| #define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) |
| #define HPM_GPTMR0_BASE (0xF0000000UL) |
| #define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) |
| #define HPM_GPTMR1_BASE (0xF0004000UL) |
| #define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) |
| #define HPM_HDMA_BASE (0xF00C8000UL) |
| #define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) |
| #define HPM_I2C0_BASE (0xF0060000UL) |
| #define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) |
| #define HPM_I2C1_BASE (0xF0064000UL) |
| #define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) |
| #define HPM_I2C2_BASE (0xF0068000UL) |
| #define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) |
| #define HPM_I2C3_BASE (0xF006C000UL) |
| #define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) |
| #define HPM_IOC_BASE (0xF4040000UL) |
| #define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) |
| #define HPM_KEYM_BASE (0xF3054000UL) |
| #define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) |
| #define HPM_MBX0A_BASE (0xF00A0000UL) |
| #define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) |
| #define HPM_MBX0B_BASE (0xF00A4000UL) |
| #define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) |
| #define HPM_MCHTMR_BASE (0xE6000000UL) |
| #define HPM_MON ((MON_Type *) HPM_MON_BASE) |
| #define HPM_MON_BASE (0xF3048000UL) |
| #define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) |
| #define HPM_OTP_BASE (0xF3050000UL) |
| #define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) |
| #define HPM_PCFG_BASE (0xF4104000UL) |
| #define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE) |
| #define HPM_PDGO_BASE (0xF4134000UL) |
| #define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) |
| #define HPM_PEWDG_BASE (0xF4128000UL) |
| #define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) |
| #define HPM_PGPIO_BASE (0xF411C000UL) |
| #define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) |
| #define HPM_PGPR0_BASE (0xF4110000UL) |
| #define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) |
| #define HPM_PGPR1_BASE (0xF4114000UL) |
| #define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) |
| #define HPM_PIOC_BASE (0xF4118000UL) |
| #define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) |
| #define HPM_PLIC_BASE (0xE4000000UL) |
| #define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) |
| #define HPM_PLICSW_BASE (0xE6400000UL) |
| #define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) |
| #define HPM_PLLCTLV2_BASE (0xF40C0000UL) |
| #define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) |
| #define HPM_PPOR_BASE (0xF4100000UL) |
| #define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) |
| #define HPM_PTMR_BASE (0xF4120000UL) |
| #define HPM_PUART ((UART_Type *) HPM_PUART_BASE) |
| #define HPM_PUART_BASE (0xF4124000UL) |
| #define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) |
| #define HPM_SEC_BASE (0xF3044000UL) |
| #define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) |
| #define HPM_SPI0_BASE (0xF0070000UL) |
| #define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) |
| #define HPM_SPI1_BASE (0xF0074000UL) |
| #define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) |
| #define HPM_SPI2_BASE (0xF0078000UL) |
| #define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) |
| #define HPM_SPI3_BASE (0xF007C000UL) |
| #define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) |
| #define HPM_SYNT_BASE (0xF0328000UL) |
| #define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) |
| #define HPM_SYSCTL_BASE (0xF4000000UL) |
| #define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) |
| #define HPM_TRGM0_BASE (0xF033C000UL) |
| #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) |
| #define HPM_TSNS_BASE (0xF0090000UL) |
| #define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) |
| #define HPM_UART0_BASE (0xF0040000UL) |
| #define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) |
| #define HPM_UART1_BASE (0xF0044000UL) |
| #define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) |
| #define HPM_UART2_BASE (0xF0048000UL) |
| #define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) |
| #define HPM_UART3_BASE (0xF004C000UL) |
| #define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) |
| #define HPM_USB0_BASE (0xF300C000UL) |
1.9.1