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HPM SDK
HPMicro Software Development Kit
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HPM SDK
HPMicro Software Development Kit
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#include "hpm_soc_irq.h"#include "hpm_common.h"#include "hpm_gpio_regs.h"#include "hpm_plic_regs.h"#include "hpm_mchtmr_regs.h"#include "hpm_plic_sw_regs.h"#include "hpm_crc_regs.h"#include "hpm_uart_regs.h"#include "hpm_i2c_regs.h"#include "hpm_spi_regs.h"#include "hpm_gptmr_regs.h"#include "hpm_mbx_regs.h"#include "hpm_ewdg_regs.h"#include "hpm_dmamux_regs.h"#include "hpm_dmav2_regs.h"#include "hpm_gpiom_regs.h"#include "hpm_adc16_regs.h"#include "hpm_i2s_regs.h"#include "hpm_dao_regs.h"#include "hpm_pdm_regs.h"#include "hpm_smix_regs.h"#include "hpm_mcan_regs.h"#include "hpm_ptpc_regs.h"#include "hpm_lcdc_regs.h"#include "hpm_cam_regs.h"#include "hpm_pdma_regs.h"#include "hpm_jpeg_regs.h"#include "hpm_gwc_regs.h"#include "hpm_mipi_dsi_regs.h"#include "hpm_mipi_csi_regs.h"#include "hpm_lvb_regs.h"#include "hpm_pixelmux_regs.h"#include "hpm_lcb_regs.h"#include "hpm_gpu_regs.h"#include "hpm_enet_regs.h"#include "hpm_usb_regs.h"#include "hpm_sdxc_regs.h"#include "hpm_ddrctl_regs.h"#include "hpm_ffa_regs.h"#include "hpm_sdp_regs.h"#include "hpm_sec_regs.h"#include "hpm_mon_regs.h"#include "hpm_rng_regs.h"#include "hpm_otp_regs.h"#include "hpm_keym_regs.h"#include "hpm_sysctl_regs.h"#include "hpm_ioc_regs.h"#include "hpm_pllctlv2_regs.h"#include "hpm_ppor_regs.h"#include "hpm_pcfg_regs.h"#include "hpm_pgpr_regs.h"#include "hpm_vad_regs.h"#include "hpm_mipi_dsi_phy_regs.h"#include "hpm_mipi_csi_phy_regs.h"#include "hpm_ddrphy_regs.h"#include "hpm_tsns_regs.h"#include "hpm_bacc_regs.h"#include "hpm_bpor_regs.h"#include "hpm_bcfg_regs.h"#include "hpm_bgpr_regs.h"#include "hpm_rtc_regs.h"#include "hpm_bsec_regs.h"#include "hpm_bkey_regs.h"#include "hpm_bmon_regs.h"#include "hpm_tamp_regs.h"#include "hpm_mono_regs.h"#include "riscv/riscv_core.h"#include "hpm_csr_regs.h"#include "hpm_interrupt.h"#include "hpm_misc.h"#include "hpm_otp_table.h"#include "hpm_dmamux_src.h"#include "hpm_iomux.h"#include "hpm_pmic_iomux.h"#include "hpm_batt_iomux.h"Go to the source code of this file.
| #define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) |
| #define HPM_ADC0_BASE (0xF00E0000UL) |
| #define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) |
| #define HPM_BACC_BASE (0xF4200000UL) |
| #define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) |
| #define HPM_BCFG_BASE (0xF4208000UL) |
| #define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) |
| #define HPM_BGPIO_BASE (0xF4214000UL) |
| #define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) |
| #define HPM_BGPR_BASE (0xF4218000UL) |
| #define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) |
| #define HPM_BIOC_BASE (0xF4210000UL) |
| #define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) |
| #define HPM_BKEY_BASE (0xF4248000UL) |
| #define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) |
| #define HPM_BMON_BASE (0xF424C000UL) |
| #define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) |
| #define HPM_BPOR_BASE (0xF4204000UL) |
| #define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) |
| #define HPM_BSEC_BASE (0xF4240000UL) |
| #define HPM_CAM0 ((CAM_Type *) HPM_CAM0_BASE) |
| #define HPM_CAM0_BASE (0xF1008000UL) |
| #define HPM_CAM1 ((CAM_Type *) HPM_CAM1_BASE) |
| #define HPM_CAM1_BASE (0xF100C000UL) |
| #define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) |
| #define HPM_CRC_BASE (0xF000C000UL) |
| #define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) |
| #define HPM_DAO_BASE (0xF0210000UL) |
| #define HPM_DDRCTL ((DDRCTL_Type *) HPM_DDRCTL_BASE) |
| #define HPM_DDRCTL_BASE (0xF3010000UL) |
| #define HPM_DDRPHY ((DDRPHY_Type *) HPM_DDRPHY_BASE) |
| #define HPM_DDRPHY_BASE (0xF4150000UL) |
| #define HPM_DM_BASE (0x30000000UL) |
| #define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) |
| #define HPM_DMAMUX_BASE (0xF00C4000UL) |
| #define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) |
| #define HPM_ENET0_BASE (0xF1100000UL) |
| #define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) |
| #define HPM_EWDG0_BASE (0xF00B0000UL) |
| #define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) |
| #define HPM_EWDG1_BASE (0xF00B4000UL) |
| #define HPM_FFA ((FFA_Type *) HPM_FFA_BASE) |
| #define HPM_FFA_BASE (0xF3018000UL) |
| #define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) |
| #define HPM_FGPIO_BASE (0xC0000UL) |
| #define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) |
| #define HPM_GPIO0_BASE (0xF00D0000UL) |
| #define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) |
| #define HPM_GPIOM_BASE (0xF00D8000UL) |
| #define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) |
| #define HPM_GPTMR0_BASE (0xF0080000UL) |
| #define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) |
| #define HPM_GPTMR1_BASE (0xF0084000UL) |
| #define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) |
| #define HPM_GPTMR2_BASE (0xF0088000UL) |
| #define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) |
| #define HPM_GPTMR3_BASE (0xF008C000UL) |
| #define HPM_GPTMR4 ((GPTMR_Type *) HPM_GPTMR4_BASE) |
| #define HPM_GPTMR4_BASE (0xF0090000UL) |
| #define HPM_GPTMR5 ((GPTMR_Type *) HPM_GPTMR5_BASE) |
| #define HPM_GPTMR5_BASE (0xF0094000UL) |
| #define HPM_GPTMR6 ((GPTMR_Type *) HPM_GPTMR6_BASE) |
| #define HPM_GPTMR6_BASE (0xF0098000UL) |
| #define HPM_GPTMR7 ((GPTMR_Type *) HPM_GPTMR7_BASE) |
| #define HPM_GPTMR7_BASE (0xF009C000UL) |
| #define HPM_GPU ((GPU_Type *) HPM_GPU_BASE) |
| #define HPM_GPU_BASE (0xF1080000UL) |
| #define HPM_GWC0 ((GWC_Type *) HPM_GWC0_BASE) |
| #define HPM_GWC0_BASE (0xF1018000UL) |
| #define HPM_GWC1 ((GWC_Type *) HPM_GWC1_BASE) |
| #define HPM_GWC1_BASE (0xF101C000UL) |
| #define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) |
| #define HPM_HDMA_BASE (0xF00C8000UL) |
| #define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) |
| #define HPM_I2C0_BASE (0xF0060000UL) |
| #define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) |
| #define HPM_I2C1_BASE (0xF0064000UL) |
| #define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) |
| #define HPM_I2C2_BASE (0xF0068000UL) |
| #define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) |
| #define HPM_I2C3_BASE (0xF006C000UL) |
| #define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) |
| #define HPM_I2S0_BASE (0xF0200000UL) |
| #define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) |
| #define HPM_I2S1_BASE (0xF0204000UL) |
| #define HPM_I2S2 ((I2S_Type *) HPM_I2S2_BASE) |
| #define HPM_I2S2_BASE (0xF0208000UL) |
| #define HPM_I2S3 ((I2S_Type *) HPM_I2S3_BASE) |
| #define HPM_I2S3_BASE (0xF020C000UL) |
| #define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) |
| #define HPM_IOC_BASE (0xF4040000UL) |
| #define HPM_JPEG ((JPEG_Type *) HPM_JPEG_BASE) |
| #define HPM_JPEG_BASE (0xF1014000UL) |
| #define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) |
| #define HPM_KEYM_BASE (0xF3054000UL) |
| #define HPM_LCB ((LCB_Type *) HPM_LCB_BASE) |
| #define HPM_LCB_BASE (0xF1038000UL) |
| #define HPM_LCDC ((LCDC_Type *) HPM_LCDC_BASE) |
| #define HPM_LCDC1 ((LCDC_Type *) HPM_LCDC1_BASE) |
| #define HPM_LCDC1_BASE (0xF1004000UL) |
| #define HPM_LCDC_BASE (0xF1000000UL) |
| #define HPM_LVB ((LVB_Type *) HPM_LVB_BASE) |
| #define HPM_LVB_BASE (0xF1030000UL) |
| #define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) |
| #define HPM_MBX0A_BASE (0xF00A0000UL) |
| #define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) |
| #define HPM_MBX0B_BASE (0xF00A4000UL) |
| #define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) |
| #define HPM_MBX1A_BASE (0xF00A8000UL) |
| #define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) |
| #define HPM_MBX1B_BASE (0xF00AC000UL) |
| #define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) |
| #define HPM_MCAN0_BASE (0xF0280000UL) |
| #define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) |
| #define HPM_MCAN1_BASE (0xF0284000UL) |
| #define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) |
| #define HPM_MCAN2_BASE (0xF0288000UL) |
| #define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) |
| #define HPM_MCAN3_BASE (0xF028C000UL) |
| #define HPM_MCAN4 ((MCAN_Type *) HPM_MCAN4_BASE) |
| #define HPM_MCAN4_BASE (0xF0290000UL) |
| #define HPM_MCAN5 ((MCAN_Type *) HPM_MCAN5_BASE) |
| #define HPM_MCAN5_BASE (0xF0294000UL) |
| #define HPM_MCAN6 ((MCAN_Type *) HPM_MCAN6_BASE) |
| #define HPM_MCAN6_BASE (0xF0298000UL) |
| #define HPM_MCAN7 ((MCAN_Type *) HPM_MCAN7_BASE) |
| #define HPM_MCAN7_BASE (0xF029C000UL) |
| #define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) |
| #define HPM_MCHTMR_BASE (0xE6000000UL) |
| #define HPM_MIPI_CSI0 ((MIPI_CSI_Type *) HPM_MIPI_CSI0_BASE) |
| #define HPM_MIPI_CSI0_BASE (0xF1028000UL) |
| #define HPM_MIPI_CSI1 ((MIPI_CSI_Type *) HPM_MIPI_CSI1_BASE) |
| #define HPM_MIPI_CSI1_BASE (0xF102C000UL) |
| #define HPM_MIPI_CSI_PHY0 ((MIPI_CSI_PHY_Type *) HPM_MIPI_CSI_PHY0_BASE) |
| #define HPM_MIPI_CSI_PHY0_BASE (0xF4148000UL) |
| #define HPM_MIPI_CSI_PHY1 ((MIPI_CSI_PHY_Type *) HPM_MIPI_CSI_PHY1_BASE) |
| #define HPM_MIPI_CSI_PHY1_BASE (0xF414C000UL) |
| #define HPM_MIPI_DSI0 ((MIPI_DSI_Type *) HPM_MIPI_DSI0_BASE) |
| #define HPM_MIPI_DSI0_BASE (0xF1020000UL) |
| #define HPM_MIPI_DSI1 ((MIPI_DSI_Type *) HPM_MIPI_DSI1_BASE) |
| #define HPM_MIPI_DSI1_BASE (0xF1024000UL) |
| #define HPM_MIPI_DSI_PHY0 ((MIPI_DSI_PHY_Type *) HPM_MIPI_DSI_PHY0_BASE) |
| #define HPM_MIPI_DSI_PHY0_BASE (0xF4140000UL) |
| #define HPM_MIPI_DSI_PHY1 ((MIPI_DSI_PHY_Type *) HPM_MIPI_DSI_PHY1_BASE) |
| #define HPM_MIPI_DSI_PHY1_BASE (0xF4144000UL) |
| #define HPM_MON ((MON_Type *) HPM_MON_BASE) |
| #define HPM_MON_BASE (0xF3048000UL) |
| #define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) |
| #define HPM_MONO_BASE (0xF4254000UL) |
| #define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) |
| #define HPM_NTMR0_BASE (0xF1110000UL) |
| #define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) |
| #define HPM_OTP_BASE (0xF3050000UL) |
| #define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) |
| #define HPM_PCFG_BASE (0xF4104000UL) |
| #define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) |
| #define HPM_PDM_BASE (0xF0214000UL) |
| #define HPM_PDMA ((PDMA_Type *) HPM_PDMA_BASE) |
| #define HPM_PDMA_BASE (0xF1010000UL) |
| #define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) |
| #define HPM_PEWDG_BASE (0xF4128000UL) |
| #define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) |
| #define HPM_PGPIO_BASE (0xF411C000UL) |
| #define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) |
| #define HPM_PGPR0_BASE (0xF4110000UL) |
| #define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) |
| #define HPM_PGPR1_BASE (0xF4114000UL) |
| #define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) |
| #define HPM_PIOC_BASE (0xF4118000UL) |
| #define HPM_PIXEL_MUX ((PIXELMUX_Type *) HPM_PIXEL_MUX_BASE) |
| #define HPM_PIXEL_MUX_BASE (0xF1034000UL) |
| #define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) |
| #define HPM_PLIC_BASE (0xE4000000UL) |
| #define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) |
| #define HPM_PLICSW_BASE (0xE6400000UL) |
| #define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) |
| #define HPM_PLLCTLV2_BASE (0xF40C0000UL) |
| #define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) |
| #define HPM_PPOR_BASE (0xF4100000UL) |
| #define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) |
| #define HPM_PTMR_BASE (0xF4120000UL) |
| #define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) |
| #define HPM_PTPC_BASE (0xF02FC000UL) |
| #define HPM_PUART ((UART_Type *) HPM_PUART_BASE) |
| #define HPM_PUART_BASE (0xF4124000UL) |
| #define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) |
| #define HPM_RNG_BASE (0xF304C000UL) |
| #define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) |
| #define HPM_RTC_BASE (0xF4244000UL) |
| #define HPM_RTCSHW ((RTC_Type *) HPM_RTCSHW_BASE) |
| #define HPM_RTCSHW_BASE (0xF421C000UL) |
| #define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) |
| #define HPM_SDP_BASE (0xF3040000UL) |
| #define HPM_SDXC0 ((SDXC_Type *) HPM_SDXC0_BASE) |
| #define HPM_SDXC0_BASE (0xF1130000UL) |
| #define HPM_SDXC1 ((SDXC_Type *) HPM_SDXC1_BASE) |
| #define HPM_SDXC1_BASE (0xF1134000UL) |
| #define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) |
| #define HPM_SEC_BASE (0xF3044000UL) |
| #define HPM_SMIX ((SMIX_Type *) HPM_SMIX_BASE) |
| #define HPM_SMIX_BASE (0xF0218000UL) |
| #define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) |
| #define HPM_SPI0_BASE (0xF0070000UL) |
| #define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) |
| #define HPM_SPI1_BASE (0xF0074000UL) |
| #define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) |
| #define HPM_SPI2_BASE (0xF0078000UL) |
| #define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) |
| #define HPM_SPI3_BASE (0xF007C000UL) |
| #define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) |
| #define HPM_SYSCTL_BASE (0xF4000000UL) |
| #define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) |
| #define HPM_TAMP_BASE (0xF4250000UL) |
| #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) |
| #define HPM_TSNS_BASE (0xF4154000UL) |
| #define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) |
| #define HPM_UART0_BASE (0xF0040000UL) |
| #define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) |
| #define HPM_UART1_BASE (0xF0044000UL) |
| #define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) |
| #define HPM_UART2_BASE (0xF0048000UL) |
| #define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) |
| #define HPM_UART3_BASE (0xF004C000UL) |
| #define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) |
| #define HPM_UART4_BASE (0xF0050000UL) |
| #define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) |
| #define HPM_UART5_BASE (0xF0054000UL) |
| #define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) |
| #define HPM_UART6_BASE (0xF0058000UL) |
| #define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) |
| #define HPM_UART7_BASE (0xF005C000UL) |
| #define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) |
| #define HPM_USB0_BASE (0xF1120000UL) |
| #define HPM_VAD ((VAD_Type *) HPM_VAD_BASE) |
| #define HPM_VAD_BASE (0xF412C000UL) |
| #define HPM_XDMA ((DMAV2_Type *) HPM_XDMA_BASE) |
| #define HPM_XDMA_BASE (0xF3008000UL) |
1.9.1