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HPM SDK
HPMicro Software Development Kit
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HPM SDK
HPMicro Software Development Kit
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#include "hpm_soc_irq.h"#include "hpm_common.h"#include "hpm_gpio_regs.h"#include "hpm_plic_regs.h"#include "hpm_mchtmr_regs.h"#include "hpm_plic_sw_regs.h"#include "hpm_gptmr_regs.h"#include "hpm_uart_regs.h"#include "hpm_i2c_regs.h"#include "hpm_spi_regs.h"#include "hpm_crc_regs.h"#include "hpm_tsns_regs.h"#include "hpm_mbx_regs.h"#include "hpm_ewdg_regs.h"#include "hpm_dmamux_regs.h"#include "hpm_dmav2_regs.h"#include "hpm_ppi_regs.h"#include "hpm_gpiom_regs.h"#include "hpm_lobs_regs.h"#include "hpm_adc16_regs.h"#include "hpm_dac_regs.h"#include "hpm_acmp_regs.h"#include "hpm_i2s_regs.h"#include "hpm_dao_regs.h"#include "hpm_pdm_regs.h"#include "hpm_mcan_regs.h"#include "hpm_ptpc_regs.h"#include "hpm_qeiv2_regs.h"#include "hpm_qeov2_regs.h"#include "hpm_pwmv2_regs.h"#include "hpm_rdc_regs.h"#include "hpm_sdm_regs.h"#include "hpm_plb_regs.h"#include "hpm_synt_regs.h"#include "hpm_sei_regs.h"#include "hpm_trgm_regs.h"#include "hpm_mtgv2_regs.h"#include "hpm_vsc_regs.h"#include "hpm_clc_regs.h"#include "hpm_enet_regs.h"#include "hpm_usb_regs.h"#include "hpm_femc_regs.h"#include "hpm_ffa_regs.h"#include "hpm_sdp_regs.h"#include "hpm_psec_regs.h"#include "hpm_pmon_regs.h"#include "hpm_rng_regs.h"#include "hpm_keym_regs.h"#include "hpm_otp_regs.h"#include "hpm_sysctl_regs.h"#include "hpm_ioc_regs.h"#include "hpm_pllctlv2_regs.h"#include "hpm_ppor_regs.h"#include "hpm_pcfg_regs.h"#include "hpm_pdgo_regs.h"#include "hpm_pgpr_regs.h"#include "riscv/riscv_core.h"#include "hpm_csr_regs.h"#include "hpm_interrupt.h"#include "hpm_misc.h"#include "hpm_otp_table.h"#include "hpm_dmamux_src.h"#include "hpm_trgmmux_src.h"#include "hpm_iomux.h"#include "hpm_pmic_iomux.h"Go to the source code of this file.
| #define HPM_ACMP0 ((ACMP_Type *) HPM_ACMP0_BASE) |
| #define HPM_ACMP0_BASE (0xF0130000UL) |
| #define HPM_ACMP1 ((ACMP_Type *) HPM_ACMP1_BASE) |
| #define HPM_ACMP1_BASE (0xF0134000UL) |
| #define HPM_ACMP2 ((ACMP_Type *) HPM_ACMP2_BASE) |
| #define HPM_ACMP2_BASE (0xF0138000UL) |
| #define HPM_ACMP3 ((ACMP_Type *) HPM_ACMP3_BASE) |
| #define HPM_ACMP3_BASE (0xF013C000UL) |
| #define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) |
| #define HPM_ADC0_BASE (0xF0100000UL) |
| #define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) |
| #define HPM_ADC1_BASE (0xF0104000UL) |
| #define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE) |
| #define HPM_ADC2_BASE (0xF0108000UL) |
| #define HPM_ADC3 ((ADC16_Type *) HPM_ADC3_BASE) |
| #define HPM_ADC3_BASE (0xF010C000UL) |
| #define HPM_CLC0 ((CLC_Type *) HPM_CLC0_BASE) |
| #define HPM_CLC0_BASE (0xF04B0000UL) |
| #define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) |
| #define HPM_CRC_BASE (0xF0080000UL) |
| #define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE) |
| #define HPM_DAC0_BASE (0xF0120000UL) |
| #define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE) |
| #define HPM_DAC1_BASE (0xF0124000UL) |
| #define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) |
| #define HPM_DAO_BASE (0xF0150000UL) |
| #define HPM_DM_BASE (0x30000000UL) |
| #define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) |
| #define HPM_DMAMUX_BASE (0xF00C4000UL) |
| #define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) |
| #define HPM_ENET0_BASE (0xF1400000UL) |
| #define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) |
| #define HPM_EWDG0_BASE (0xF00B0000UL) |
| #define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) |
| #define HPM_EWDG1_BASE (0xF00B4000UL) |
| #define HPM_EWDG2 ((EWDG_Type *) HPM_EWDG2_BASE) |
| #define HPM_EWDG2_BASE (0xF00B8000UL) |
| #define HPM_EWDG3 ((EWDG_Type *) HPM_EWDG3_BASE) |
| #define HPM_EWDG3_BASE (0xF00BC000UL) |
| #define HPM_FEMC ((FEMC_Type *) HPM_FEMC_BASE) |
| #define HPM_FEMC_BASE (0xF300C000UL) |
| #define HPM_FFA ((FFA_Type *) HPM_FFA_BASE) |
| #define HPM_FFA_BASE (0xF3108000UL) |
| #define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) |
| #define HPM_FGPIO_BASE (0x300000UL) |
| #define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) |
| #define HPM_GPIO0_BASE (0xF00D0000UL) |
| #define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE) |
| #define HPM_GPIO1_BASE (0xF00D4000UL) |
| #define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) |
| #define HPM_GPIOM_BASE (0xF00D8000UL) |
| #define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) |
| #define HPM_GPTMR0_BASE (0xF0000000UL) |
| #define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) |
| #define HPM_GPTMR1_BASE (0xF0004000UL) |
| #define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) |
| #define HPM_GPTMR2_BASE (0xF0008000UL) |
| #define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) |
| #define HPM_GPTMR3_BASE (0xF000C000UL) |
| #define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) |
| #define HPM_HDMA_BASE (0xF00C8000UL) |
| #define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) |
| #define HPM_I2C0_BASE (0xF0060000UL) |
| #define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) |
| #define HPM_I2C1_BASE (0xF0064000UL) |
| #define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) |
| #define HPM_I2C2_BASE (0xF0068000UL) |
| #define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) |
| #define HPM_I2C3_BASE (0xF006C000UL) |
| #define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) |
| #define HPM_I2S0_BASE (0xF0140000UL) |
| #define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) |
| #define HPM_I2S1_BASE (0xF0144000UL) |
| #define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) |
| #define HPM_IOC_BASE (0xF4040000UL) |
| #define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) |
| #define HPM_KEYM_BASE (0xF3154000UL) |
| #define HPM_LOBS ((LOBS_Type *) HPM_LOBS_BASE) |
| #define HPM_LOBS_BASE (0xF00DC000UL) |
| #define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) |
| #define HPM_MBX0A_BASE (0xF00A0000UL) |
| #define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) |
| #define HPM_MBX0B_BASE (0xF00A4000UL) |
| #define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) |
| #define HPM_MBX1A_BASE (0xF00A8000UL) |
| #define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) |
| #define HPM_MBX1B_BASE (0xF00AC000UL) |
| #define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) |
| #define HPM_MCAN0_BASE (0xF0300000UL) |
| #define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) |
| #define HPM_MCAN1_BASE (0xF0304000UL) |
| #define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) |
| #define HPM_MCAN2_BASE (0xF0308000UL) |
| #define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) |
| #define HPM_MCAN3_BASE (0xF030C000UL) |
| #define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) |
| #define HPM_MCHTMR_BASE (0xE6000000UL) |
| #define HPM_MTG0 ((MTGV2_Type *) HPM_MTG0_BASE) |
| #define HPM_MTG0_BASE (0xF0490000UL) |
| #define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) |
| #define HPM_NTMR0_BASE (0xF1410000UL) |
| #define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) |
| #define HPM_OTP_BASE (0xF3158000UL) |
| #define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) |
| #define HPM_PCFG_BASE (0xF4104000UL) |
| #define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE) |
| #define HPM_PDGO_BASE (0xF4134000UL) |
| #define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) |
| #define HPM_PDM_BASE (0xF0154000UL) |
| #define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) |
| #define HPM_PEWDG_BASE (0xF4128000UL) |
| #define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) |
| #define HPM_PGPIO_BASE (0xF411C000UL) |
| #define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) |
| #define HPM_PGPR0_BASE (0xF4138000UL) |
| #define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) |
| #define HPM_PGPR1_BASE (0xF413C000UL) |
| #define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) |
| #define HPM_PIOC_BASE (0xF4118000UL) |
| #define HPM_PLB ((PLB_Type *) HPM_PLB_BASE) |
| #define HPM_PLB_BASE (0xF0460000UL) |
| #define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) |
| #define HPM_PLIC_BASE (0xE4000000UL) |
| #define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) |
| #define HPM_PLICSW_BASE (0xE6400000UL) |
| #define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) |
| #define HPM_PLLCTLV2_BASE (0xF40C0000UL) |
| #define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) |
| #define HPM_PMON_BASE (0xF3148000UL) |
| #define HPM_PPI ((PPI_Type *) HPM_PPI_BASE) |
| #define HPM_PPI_BASE (0xF00CC000UL) |
| #define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) |
| #define HPM_PPOR_BASE (0xF4100000UL) |
| #define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) |
| #define HPM_PSEC_BASE (0xF3144000UL) |
| #define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) |
| #define HPM_PTMR_BASE (0xF4120000UL) |
| #define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) |
| #define HPM_PTPC_BASE (0xF037C000UL) |
| #define HPM_PUART ((UART_Type *) HPM_PUART_BASE) |
| #define HPM_PUART_BASE (0xF4124000UL) |
| #define HPM_PWM0 ((PWMV2_Type *) HPM_PWM0_BASE) |
| #define HPM_PWM0_BASE (0xF0420000UL) |
| #define HPM_PWM1 ((PWMV2_Type *) HPM_PWM1_BASE) |
| #define HPM_PWM1_BASE (0xF0424000UL) |
| #define HPM_PWM2 ((PWMV2_Type *) HPM_PWM2_BASE) |
| #define HPM_PWM2_BASE (0xF0428000UL) |
| #define HPM_PWM3 ((PWMV2_Type *) HPM_PWM3_BASE) |
| #define HPM_PWM3_BASE (0xF042C000UL) |
| #define HPM_QEI0 ((QEIV2_Type *) HPM_QEI0_BASE) |
| #define HPM_QEI0_BASE (0xF0400000UL) |
| #define HPM_QEI1 ((QEIV2_Type *) HPM_QEI1_BASE) |
| #define HPM_QEI1_BASE (0xF0404000UL) |
| #define HPM_QEO0 ((QEOV2_Type *) HPM_QEO0_BASE) |
| #define HPM_QEO0_BASE (0xF0410000UL) |
| #define HPM_QEO1 ((QEOV2_Type *) HPM_QEO1_BASE) |
| #define HPM_QEO1_BASE (0xF0414000UL) |
| #define HPM_RDC0 ((RDC_Type *) HPM_RDC0_BASE) |
| #define HPM_RDC0_BASE (0xF0440000UL) |
| #define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) |
| #define HPM_RNG_BASE (0xF314C000UL) |
| #define HPM_SDM0 ((SDM_Type *) HPM_SDM0_BASE) |
| #define HPM_SDM0_BASE (0xF0450000UL) |
| #define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) |
| #define HPM_SDP_BASE (0xF3140000UL) |
| #define HPM_SEI ((SEI_Type *) HPM_SEI_BASE) |
| #define HPM_SEI_BASE (0xF0470000UL) |
| #define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) |
| #define HPM_SPI0_BASE (0xF0070000UL) |
| #define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) |
| #define HPM_SPI1_BASE (0xF0074000UL) |
| #define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) |
| #define HPM_SPI2_BASE (0xF0078000UL) |
| #define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) |
| #define HPM_SPI3_BASE (0xF007C000UL) |
| #define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) |
| #define HPM_SYNT_BASE (0xF0464000UL) |
| #define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) |
| #define HPM_SYSCTL_BASE (0xF4000000UL) |
| #define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) |
| #define HPM_TRGM0_BASE (0xF047C000UL) |
| #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) |
| #define HPM_TSNS_BASE (0xF0090000UL) |
| #define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) |
| #define HPM_UART0_BASE (0xF0040000UL) |
| #define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) |
| #define HPM_UART1_BASE (0xF0044000UL) |
| #define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) |
| #define HPM_UART2_BASE (0xF0048000UL) |
| #define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) |
| #define HPM_UART3_BASE (0xF004C000UL) |
| #define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) |
| #define HPM_UART4_BASE (0xF0050000UL) |
| #define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) |
| #define HPM_UART5_BASE (0xF0054000UL) |
| #define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) |
| #define HPM_UART6_BASE (0xF0058000UL) |
| #define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) |
| #define HPM_UART7_BASE (0xF005C000UL) |
| #define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) |
| #define HPM_USB0_BASE (0xF1420000UL) |
| #define HPM_VSC0 ((VSC_Type *) HPM_VSC0_BASE) |
| #define HPM_VSC0_BASE (0xF04A0000UL) |
| #define HPM_XDMA ((DMAV2_Type *) HPM_XDMA_BASE) |
| #define HPM_XDMA_BASE (0xF3100000UL) |
1.9.1