#include "hpm_soc.h"
#include "hpm_soc_ip_feature.h"

Macros
#define	HPM_L1C_CACHE_SIZE (uint32_t)(16 * SIZE_1KB)

#define	HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE)

#define	HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE)

#define	HPM_L1C_CACHELINE_SIZE (32)

#define	HPM_L1C_CACHELINES_PER_WAY (128)

#define	HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U))

#define	HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U)

#define	PLIC_SUPPORT_EDGE_TRIGGER (1)

#define	PMP_SUPPORT_PMA (0)

#define	I2C_SOC_FIFO_SIZE (4U)

#define	I2C_SOC_TRANSFER_COUNT_MAX (4096U)

#define	PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U)

#define	PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U)

#define	PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125)

#define	PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U)

#define	PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U)

#define	PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U)

#define	PLLCTL_SOC_PLL_MAX_COUNT (2U)

#define	PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL)

#define	PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) \|\| ((x) == 2)) ? 1 : 0)

#define	PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) \|\| ((x) == 2)) ? 1 : 0)

#define	PWM_SOC_PWM_MAX_COUNT (8U)

#define	PWM_SOC_CMP_MAX_COUNT (24U)

#define	PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U)

#define	DMA_SOC_TRANSFER_WIDTH_MAX(x) (DMA_TRANSFER_WIDTH_WORD)

#define	DMA_SOC_TRANSFER_PER_BURST_MAX(x) (DMA_NUM_TRANSFER_PER_BURST_128T)

#define	DMA_SOC_CHANNEL_NUM (32U)

#define	DMA_SOC_MAX_COUNT (1U)

#define	DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (DMAMUX_MUXCFG_HDMA_MUX0 + n)

#define	DMA_SOC_HAS_IDLE_FLAG (1U)

#define	DMAMUX_SOC_WRITEONLY (1U)

#define	USB_SOC_MAX_COUNT (1U)

#define	USB_SOC_DCD_QTD_NEXT_INVALID (1U)

#define	USB_SOC_DCD_QHD_BUFFER_COUNT (5U)

#define	USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U)

#define	USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U)

#define	USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT)

#define	USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U)

#define	USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U)

#define	USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U)

#define	ADC_SOC_IP_VERSION (3U)

#define	ADC_SOC_SEQ_MAX_LEN (16U)

#define	ADC_SOC_SEQ_HCFG_EN (1U)

#define	ADC_SOC_MAX_TRIG_CH_LEN (4U)

#define	ADC_SOC_MAX_TRIG_CH_NUM (11U)

#define	ADC_SOC_DMA_ADDR_ALIGNMENT (4U)

#define	ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U)

#define	ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U)

#define	ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U)

#define	ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U)

#define	ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U)

#define	ADC16_SOC_PARAMS_LEN (34U)

#define	ADC16_SOC_MAX_CH_NUM (15U)

#define	ADC16_SOC_MAX_SAMPLE_VALUE (65535U)

#define	ADC16_SOC_MAX_CONV_CLK_NUM (21U)

#define	SYSCTL_SOC_CPU_GPR_COUNT (14U)

#define	SYSCTL_SOC_MONITOR_SLICE_COUNT (4U)

#define	PTPC_SOC_TIMER_MAX_COUNT (2U)

#define	SDP_REGISTER_DESCRIPTOR_COUNT (1U)

#define	SDP_HAS_SM3_SUPPORT (1U)

#define	SDP_HAS_SM4_SUPPORT (1U)

#define	SOC_HAS_S_MODE (0U)

#define	DAC_SOC_BUFF_ALIGNED_SIZE (32U)

#define	DAC_SOC_MAX_DATA (4095U)

#define	DAC_SOC_MAX_BUFF_COUNT (65536U)

#define	DAC_SOC_MAX_OUTPUT_FREQ (1000000UL)

#define	UART_SOC_FIFO_SIZE (16U)

#define	UART_SOC_OVERSAMPLE_MAX (30U) /* only support 30 oversample rate for rx idle detection */

#define	SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU)

#define	SPI_SOC_FIFO_DEPTH (8U)

#define	OTP_SOC_UUID_IDX (88U)

#define	OTP_SOC_UUID_LEN (16U) /* in bytes */

#define	PWM_SOC_HRPWM_SUPPORT (0U)

#define	PWM_SOC_SHADOW_TRIG_SUPPORT (0U)

#define	PWM_SOC_TIMER_RESET_SUPPORT (1U)

#define	TRGM_SOC_HAS_FILTER_SHIFT (1U)

#define	TRGM_SOC_HAS_DMAMUX_EN (1U)

#define	TRGM_SOC_HAS_ADC_MATRIX_SEL (1U)

#define	TRGM_SOC_HAS_DAC_MATRIX_SEL (1U)

#define	TRGM_SOC_HAS_POS_MATRIX_SEL (1U)

#define	TRGM_SOC_TRIM_IN_GROUP_MAX (3U)

#define	TRGM_SOC_TRIM_OUT_GROUP_MAX (4U)

#define	MCAN_SOC_MAX_COUNT (4U)

#define	MCAN_SOC_MSG_BUF_IN_IP (0U)

#define	MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U)

#define	CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT

#define	EWDG_SOC_CLK_DIV_VAL_MAX (5U)

#define	EWDG_SOC_OVERTIME_REG_WIDTH (16U)

#define	EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (1)

#define	SYNT_SOC_HAS_TIMESTAMP (1U)

#define	GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U)

#define	OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM (7U)

#define	PLB_SOC_TYPEA_TRGM_INPUT0 (TRGM_TRGOCFG_PLB_IN_00)

#define	PLB_SOC_TYPEA_TRGM_OUTPUT0 (HPM_TRGM0_INPUT_SRC_PLB_OUT00)

#define	PLB_SOC_TYPEB_TRGM_INPUT0 (TRGM_TRGOCFG_PLB_IN_16)

#define	PLB_SOC_TYPEB_TRGM_OUTPUT0 (HPM_TRGM0_INPUT_SRC_PLB_OUT16)

Macro Definition Documentation

◆ ADC16_SOC_MAX_CH_NUM

#define ADC16_SOC_MAX_CH_NUM (15U)

◆ ADC16_SOC_MAX_CONV_CLK_NUM

#define ADC16_SOC_MAX_CONV_CLK_NUM (21U)

◆ ADC16_SOC_MAX_SAMPLE_VALUE

#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U)

◆ ADC16_SOC_PARAMS_LEN

#define ADC16_SOC_PARAMS_LEN (34U)

◆ ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT

#define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U)

◆ ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE

#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U)

◆ ADC_SOC_DMA_ADDR_ALIGNMENT

#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U)

◆ ADC_SOC_IP_VERSION

#define ADC_SOC_IP_VERSION (3U)

◆ ADC_SOC_MAX_TRIG_CH_LEN

#define ADC_SOC_MAX_TRIG_CH_LEN (4U)

◆ ADC_SOC_MAX_TRIG_CH_NUM

#define ADC_SOC_MAX_TRIG_CH_NUM (11U)

◆ ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES

#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U)

◆ ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT

#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U)

◆ ADC_SOC_SEQ_HCFG_EN

#define ADC_SOC_SEQ_HCFG_EN (1U)

◆ ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES

#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U)

◆ ADC_SOC_SEQ_MAX_LEN

#define ADC_SOC_SEQ_MAX_LEN (16U)

◆ CAN_SOC_MAX_COUNT

#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT

◆ DAC_SOC_BUFF_ALIGNED_SIZE

#define DAC_SOC_BUFF_ALIGNED_SIZE (32U)

◆ DAC_SOC_MAX_BUFF_COUNT

#define DAC_SOC_MAX_BUFF_COUNT (65536U)

◆ DAC_SOC_MAX_DATA

#define DAC_SOC_MAX_DATA (4095U)

◆ DAC_SOC_MAX_OUTPUT_FREQ

#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL)

◆ DMA_SOC_CHANNEL_NUM

#define DMA_SOC_CHANNEL_NUM (32U)

◆ DMA_SOC_CHN_TO_DMAMUX_CHN

#define DMA_SOC_CHN_TO_DMAMUX_CHN	(	x,
		n
	)	(DMAMUX_MUXCFG_HDMA_MUX0 + n)

◆ DMA_SOC_HAS_IDLE_FLAG

#define DMA_SOC_HAS_IDLE_FLAG (1U)

◆ DMA_SOC_MAX_COUNT

#define DMA_SOC_MAX_COUNT (1U)

◆ DMA_SOC_TRANSFER_PER_BURST_MAX

#define DMA_SOC_TRANSFER_PER_BURST_MAX ( x ) (DMA_NUM_TRANSFER_PER_BURST_128T)

◆ DMA_SOC_TRANSFER_WIDTH_MAX

#define DMA_SOC_TRANSFER_WIDTH_MAX ( x ) (DMA_TRANSFER_WIDTH_WORD)

◆ DMAMUX_SOC_WRITEONLY

#define DMAMUX_SOC_WRITEONLY (1U)

◆ EWDG_SOC_CLK_DIV_VAL_MAX

#define EWDG_SOC_CLK_DIV_VAL_MAX (5U)

◆ EWDG_SOC_OVERTIME_REG_WIDTH

#define EWDG_SOC_OVERTIME_REG_WIDTH (16U)

◆ EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER

#define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (1)

◆ GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT

#define GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U)

◆ HPM_L1C_CACHE_SIZE

#define HPM_L1C_CACHE_SIZE (uint32_t)(16 * SIZE_1KB)

◆ HPM_L1C_CACHELINE_ALIGN_DOWN

#define HPM_L1C_CACHELINE_ALIGN_DOWN ( n ) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U))

◆ HPM_L1C_CACHELINE_ALIGN_UP

#define HPM_L1C_CACHELINE_ALIGN_UP ( n ) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U)

◆ HPM_L1C_CACHELINE_SIZE

#define HPM_L1C_CACHELINE_SIZE (32)

◆ HPM_L1C_CACHELINES_PER_WAY

#define HPM_L1C_CACHELINES_PER_WAY (128)

◆ HPM_L1C_DCACHE_SIZE

#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE)

◆ HPM_L1C_ICACHE_SIZE

#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE)

◆ I2C_SOC_FIFO_SIZE

#define I2C_SOC_FIFO_SIZE (4U)

◆ I2C_SOC_TRANSFER_COUNT_MAX

#define I2C_SOC_TRANSFER_COUNT_MAX (4096U)

◆ MCAN_SOC_MAX_COUNT

#define MCAN_SOC_MAX_COUNT (4U)

◆ MCAN_SOC_MSG_BUF_IN_AHB_RAM

#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U)

◆ MCAN_SOC_MSG_BUF_IN_IP

#define MCAN_SOC_MSG_BUF_IN_IP (0U)

◆ OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM

#define OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM (7U)

OPAMP

◆ OTP_SOC_UUID_IDX

#define OTP_SOC_UUID_IDX (88U)

◆ OTP_SOC_UUID_LEN

#define OTP_SOC_UUID_LEN (16U) /* in bytes */

◆ PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV

#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U)

◆ PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV

#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U)

◆ PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV

#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U)

◆ PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV

#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U)

◆ PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV

#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U)

◆ PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV

#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125)

◆ PLB_SOC_TYPEA_TRGM_INPUT0

#define PLB_SOC_TYPEA_TRGM_INPUT0 (TRGM_TRGOCFG_PLB_IN_00)

PLB

◆ PLB_SOC_TYPEA_TRGM_OUTPUT0

#define PLB_SOC_TYPEA_TRGM_OUTPUT0 (HPM_TRGM0_INPUT_SRC_PLB_OUT00)

◆ PLB_SOC_TYPEB_TRGM_INPUT0

#define PLB_SOC_TYPEB_TRGM_INPUT0 (TRGM_TRGOCFG_PLB_IN_16)

◆ PLB_SOC_TYPEB_TRGM_OUTPUT0

#define PLB_SOC_TYPEB_TRGM_OUTPUT0 (HPM_TRGM0_INPUT_SRC_PLB_OUT16)

◆ PLIC_SUPPORT_EDGE_TRIGGER

#define PLIC_SUPPORT_EDGE_TRIGGER (1)

◆ PLLCTL_SOC_PLL_HAS_DIV0

#define PLLCTL_SOC_PLL_HAS_DIV0 ( x ) ((((x) == 1) || ((x) == 2)) ? 1 : 0)

◆ PLLCTL_SOC_PLL_HAS_DIV1

#define PLLCTL_SOC_PLL_HAS_DIV1 ( x ) ((((x) == 1) || ((x) == 2)) ? 1 : 0)

◆ PLLCTL_SOC_PLL_MAX_COUNT

#define PLLCTL_SOC_PLL_MAX_COUNT (2U)

◆ PLLCTL_SOC_PLL_REFCLK_FREQ

#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL)

◆ PMP_SUPPORT_PMA

#define PMP_SUPPORT_PMA (0)

◆ PTPC_SOC_TIMER_MAX_COUNT

#define PTPC_SOC_TIMER_MAX_COUNT (2U)

◆ PWM_SOC_CMP_MAX_COUNT

#define PWM_SOC_CMP_MAX_COUNT (24U)

◆ PWM_SOC_HRPWM_SUPPORT

#define PWM_SOC_HRPWM_SUPPORT (0U)

◆ PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT

#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U)

◆ PWM_SOC_PWM_MAX_COUNT

#define PWM_SOC_PWM_MAX_COUNT (8U)

◆ PWM_SOC_SHADOW_TRIG_SUPPORT

#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U)

◆ PWM_SOC_TIMER_RESET_SUPPORT

#define PWM_SOC_TIMER_RESET_SUPPORT (1U)

◆ SDP_HAS_SM3_SUPPORT

#define SDP_HAS_SM3_SUPPORT (1U)

◆ SDP_HAS_SM4_SUPPORT

#define SDP_HAS_SM4_SUPPORT (1U)

◆ SDP_REGISTER_DESCRIPTOR_COUNT

#define SDP_REGISTER_DESCRIPTOR_COUNT (1U)

◆ SOC_HAS_S_MODE

#define SOC_HAS_S_MODE (0U)

◆ SPI_SOC_FIFO_DEPTH

#define SPI_SOC_FIFO_DEPTH (8U)

◆ SPI_SOC_TRANSFER_COUNT_MAX

#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU)

◆ SYNT_SOC_HAS_TIMESTAMP

#define SYNT_SOC_HAS_TIMESTAMP (1U)

◆ SYSCTL_SOC_CPU_GPR_COUNT

#define SYSCTL_SOC_CPU_GPR_COUNT (14U)

◆ SYSCTL_SOC_MONITOR_SLICE_COUNT

#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U)

◆ TRGM_SOC_HAS_ADC_MATRIX_SEL

#define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U)

◆ TRGM_SOC_HAS_DAC_MATRIX_SEL

#define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U)

◆ TRGM_SOC_HAS_DMAMUX_EN

#define TRGM_SOC_HAS_DMAMUX_EN (1U)

◆ TRGM_SOC_HAS_FILTER_SHIFT

#define TRGM_SOC_HAS_FILTER_SHIFT (1U)

◆ TRGM_SOC_HAS_POS_MATRIX_SEL

#define TRGM_SOC_HAS_POS_MATRIX_SEL (1U)

◆ TRGM_SOC_TRIM_IN_GROUP_MAX

#define TRGM_SOC_TRIM_IN_GROUP_MAX (3U)

◆ TRGM_SOC_TRIM_OUT_GROUP_MAX

#define TRGM_SOC_TRIM_OUT_GROUP_MAX (4U)

◆ UART_SOC_FIFO_SIZE

#define UART_SOC_FIFO_SIZE (16U)

◆ UART_SOC_OVERSAMPLE_MAX

#define UART_SOC_OVERSAMPLE_MAX (30U) /* only support 30 oversample rate for rx idle detection */

◆ USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT

#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U)

◆ USB_SOC_DCD_MAX_ENDPOINT_COUNT

#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U)

◆ USB_SOC_DCD_MAX_QTD_COUNT

#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT)

◆ USB_SOC_DCD_QHD_BUFFER_COUNT

#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U)

◆ USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT

#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U)

◆ USB_SOC_DCD_QTD_NEXT_INVALID

#define USB_SOC_DCD_QTD_NEXT_INVALID (1U)

◆ USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS

#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U)

◆ USB_SOC_MAX_COUNT

#define USB_SOC_MAX_COUNT (1U)

◆ USB_SOS_DCD_MAX_QHD_COUNT

#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U)

Macros